source: ctrl/firmware/Main/SES/Wiznet/Ethernet/W5100S/w5100s.h

Last change on this file was 79, checked in by Zed, 3 months ago

DHCP client can get IP-address from fritz!box
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1//* ****************************************************************************
2//! \file w5100S.h
3//! \brief W5100S HAL Header File.
4//! \version 1.0.0
5//! \date 2018/03/29
6//! \par  Revision history
7//!       <2018/03/29> 1st Release
8//! \author Peter
9//! \copyright
10//!
11//! Copyright (c)  2013, WIZnet Co., LTD.
12//! All rights reserved.
13//!
14//! Redistribution and use in source and binary forms, with or without
15//! modification, are permitted provided that the following conditions
16//! are met:
17//!
18//!     * Redistributions of source code must retain the above copyright
19//! notice, this list of conditions and the following disclaimer.
20//!     * Redistributions in binary form must reproduce the above copyright
21//! notice, this list of conditions and the following disclaimer in the
22//! documentation and/or other materials provided with the distribution.
23//!     * Neither the name of the <ORGANIZATION> nor the names of its
24//! contributors may be used to endorse or promote products derived
25//! from this software without specific prior written permission.
26//!
27//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
31//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37//! THE POSSIBILITY OF SUCH DAMAGE.
38//
39//*****************************************************************************
40
41
42#ifndef _W5100S_H_
43#define _W5100S_H_
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <stdint.h>
50#include "wizchip_conf.h"
51
52/// \cond DOXY_APPLY_CODE
53#if   (_WIZCHIP_ == W5100S)
54/// \endcond
55
56#define _WIZCHIP_SN_BASE_  (0x0400)
57#define _WIZCHIP_SN_SIZE_  (0x0100)
58#define _WIZCHIP_IO_TXBUF_ (0x4000) /* Internal Tx buffer address of the iinchip */
59#define _WIZCHIP_IO_RXBUF_ (0x6000) /* Internal Rx buffer address of the iinchip */
60
61
62#define WIZCHIP_CREG_BLOCK                    0x00   ///< Common register block
63#define WIZCHIP_SREG_BLOCK(N)              (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N) ///< Socket N register block
64
65#define WIZCHIP_OFFSET_INC(ADDR, N)    (ADDR + N) ///< Increase offset address
66
67#if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
68   #define _W5100S_IO_BASE_     _WIZCHIP_IO_BASE_
69#elif (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
70        #define IDM_OR             ((_WIZCHIP_IO_BASE  + 0x0000))
71        #define IDM_AR0            ((_WIZCHIP_IO_BASE_ + 0x0001))
72        #define IDM_AR1            ((_WIZCHIP_IO_BASE_ + 0x0002))
73        #define IDM_DR             ((_WIZCHIP_IO_BASE_ + 0x0003))
74        #define _W5100S_IO_BASE_    0x0000
75#elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
76   #define _W5100S_IO_BASE_    0x0000
77#endif
78
79///////////////////////////////////////
80// Definition For Legacy Chip Driver //
81///////////////////////////////////////
82#define IINCHIP_READ(ADDR)                WIZCHIP_READ(ADDR)               ///< The defined for legacy chip driver
83#define IINCHIP_WRITE(ADDR,VAL)           WIZCHIP_WRITE(ADDR,VAL)          ///< The defined for legacy chip driver
84#define IINCHIP_READ_BUF(ADDR,BUF,LEN)    WIZCHIP_READ_BUF(ADDR,BUF,LEN)   ///< The defined for legacy chip driver
85#define IINCHIP_WRITE_BUF(ADDR,BUF,LEN)   WIZCHIP_WRITE(ADDR,BUF,LEN)      ///< The defined for legacy chip driver
86
87
88//-----------    defgroup --------------------------------
89
90/**
91 * @defgroup W5100S W5100S
92 * @brief WHIZCHIP register defines and I/O functions of @b W5100S.
93 *
94 * - @ref WIZCHIP_register_W5100S: @ref Common_register_group_W5100S and @ref Socket_register_group_W5100S
95 * - @ref WIZCHIP_IO_Functions_W5100S: @ref Basic_IO_function_W5100S, @ref Common_register_access_function_W5100S and @ref Special_function_W5100S
96 */
97
98 /**
99 * @defgroup WIZCHIP_register_W5100S WIZCHIP register
100 * @ingroup W5100S
101 * @brief WIZCHIP register defines register group of <b> W5100S </b>.
102 *
103 * - \ref Common_register_group_W5100S : Common register group W5100S
104 * - \ref Socket_register_group_W5100S : \c SOCKET n register group W5100S
105 */
106
107
108/**
109 * @defgroup WIZCHIP_IO_Functions_W5100S WIZCHIP I/O functions
110 * @ingroup W5100S
111 * @brief This supports the basic I/O functions for \ref WIZCHIP_register_W5100S.
112 *
113 * - <b> Basic I/O function </b> \n
114 *   WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF(), wiz_recv_data(), wiz_recv_ignore(), wiz_send_data() \n\n
115 *
116 * - \ref Common_register_group_W5100S <b>access functions</b> \n
117 *      -# @b Mode \n
118 *    getMR(), setMR()
119 *      -# @b Interrupt \n
120 *    getIR(), setIR(), getIMR(), setIMR(),
121 *      -# <b> Network Information </b> \n
122 *    getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
123 *      -# @b Retransmission \n
124 *    getRCR(), setRCR(), getRTR(), setRTR()
125 *      -# @b PPPoE \n
126 *    getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC()
127 *
128 * - \ref Socket_register_group_W5100S <b>access functions</b> \n
129 *   -# <b> SOCKET control</b> \n
130 *      getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IR(), setSn_IR()
131 *   -# <b> SOCKET information</b> \n
132 *      getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT()
133 *      getSn_MSSR(), setSn_MSSR()
134 *   -# <b> SOCKET communication </b> \n
135 *      getSn_RXMEM_SIZE(), setSn_RXMEM_SIZE(), getSn_TXMEM_SIZE(), setSn_TXMEM_SIZE() \n
136 *      getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n
137 *      getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n
138 *      getSn_TX_FSR(), getSn_RX_RSR()
139 *   -# <b> IP header field </b> \n
140 *      getSn_FRAG(), setSn_FRAG(),  getSn_TOS(), setSn_TOS() \n
141 *      getSn_TTL(), setSn_TTL()
142 */
143
144/**
145 * @defgroup Common_register_group_W5100S Common register
146 * @ingroup WIZCHIP_register_W5100S
147 * @brief Common register group\n
148 * It set the basic for the networking\n
149 * It set the configuration such as interrupt, network information, ICMP, etc.
150 * @details
151 * @sa MR : Mode register.
152 * @sa GAR, SUBR, SHAR, SIPR
153 * @sa IR, Sn_IR, _IMR_  : Interrupt.
154 * @sa _RTR_, _RCR_ : Data retransmission.
155 * @sa PTIMER, PMAGIC : PPPoE.
156 */
157
158
159 /**
160 * @defgroup Socket_register_group_W5100S Socket register
161 * @ingroup WIZCHIP_register_W5100S
162 * @brief Socket register group\n
163 * Socket register configures and control SOCKETn which is necessary to data communication.
164 * @details
165 * @sa Sn_MR, Sn_CR, Sn_IR : SOCKETn Control
166 * @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
167 * @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_FRAGR : Internet protocol.
168 * @sa Sn_RXMEM_SIZE, Sn_TXMEM_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication
169 */
170
171 /**
172 * @defgroup Basic_IO_function_W5100S Basic I/O function
173 * @ingroup WIZCHIP_IO_Functions_W5100S
174 * @brief These are basic input/output functions to read values from register or write values to register.
175 */
176
177/**
178 * @defgroup Common_register_access_function_W5100S Common register access functions
179 * @ingroup WIZCHIP_IO_Functions_W5100S
180 * @brief These are functions to access <b>common registers</b>.
181 */
182
183/**
184 * @defgroup Socket_register_access_function_W5100S Socket register access functions
185 * @ingroup WIZCHIP_IO_Functions_W5100S
186 * @brief These are functions to access <b>socket registers</b>.
187 */
188
189 /**
190 * @defgroup Special_function_W5100S Special functions
191 * @ingroup WIZCHIP_IO_Functions_W5100S
192 * @brief These are special functions to access to the PHY
193 */
194
195 //-----------------------------------------------------------------------------------
196
197//----------------------------- W5100S Common Registers IOMAP -----------------------------
198/**
199 * @ingroup Common_register_group_W5100S
200 * @brief Mode Register address(R/W)\n
201 * \ref MR is used for S/W reset, ping block mode, PPPoE mode and etc.
202 * @details Each bit of \ref MR defined as follows.
203 * <table>
204 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
205 *              <tr>  <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>AI</td> <td>IND</td> </tr>
206 * </table>
207 * - \ref MR_RST                        : Reset
208 * - \ref MR_PB                 : Ping block
209 * - \ref MR_PPPOE              : PPPoE mode
210 * - \ref MR_AI                 : Address Auto-Increment in Indirect Bus Interface
211 * - \ref MR_IND                : Indirect Bus Interface mode
212 */
213#if _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_
214   #define MR                                   (_WIZCHIP_IO_BASE_ + (0x0000))  // Mode
215#else
216   #define MR                                   (_W5100S_IO_BASE_ + (0x0000))  // Mode
217#endif
218
219/**
220 * @ingroup Common_register_group_W5100S
221 * @brief Gateway IP Register address(R/W)
222 * @details \ref GAR configures the default gateway address.
223 */
224#define GAR                             (_W5100S_IO_BASE_ + (0x0001))  // GW Address
225
226/**
227 * @ingroup Common_register_group_W5100S
228 * @brief Subnet mask Register address(R/W)
229 * @details \ref SUBR configures the subnet mask address.
230 */
231#define SUBR                            (_W5100S_IO_BASE_ + (0x0005)) // SN Mask Address
232
233/**
234 * @ingroup Common_register_group_W5100S
235 * @brief Source MAC Register address(R/W)
236 * @details \ref SHAR configures the source hardware address.
237 */
238#define SHAR                            (_W5100S_IO_BASE_ + (0x0009)) // Source Hardware Address
239
240/**
241 * @ingroup Common_register_group_W5100S
242 * @brief Source IP Register address(R/W)
243 * @details \ref SIPR configures the source IP address.
244 */
245#define SIPR                            (_W5100S_IO_BASE_ + (0x000F)) // Source IP Address
246
247// Reserved                                     (_W5100S_IO_BASE_ + (0x0013))
248// Reserved                                     (_W5100S_IO_BASE_ + (0x0014))
249
250/**
251 * @ingroup Common_register_group_W5100S
252 * @brief Interrupt Register(R/W)
253 * @details \ref IR indicates the interrupt status. Each bit of \ref IR will be still until the bit will be written to by the host.
254 * If \ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n
255 * Each bit of \ref IR defined as follows.
256 * <table>
257 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
258 *              <tr>  <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>Reserved</td> <td>S3_INT</td> <td>S2_INT</td> <td>S1_INT</td> <td>S0_INT</td> </tr>
259 * </table>
260 * - \ref IR_CONFLICT : IP conflict
261 * - \ref IR_UNREACH  : Destination unreachable
262 * - \ref IR_PPPoE       : PPPoE connection close
263 * - \ref IR_SOCK(3)  : SOCKET 3 Interrupt
264 * - \ref IR_SOCK(2)  : SOCKET 2 Interrupt
265 * - \ref IR_SOCK(1)  : SOCKET 1 Interrupt
266 * - \ref IR_SOCK(0)  : SOCKET 0 Interrupt
267 */
268#define IR                                      (_W5100S_IO_BASE_ + (0x0015)) // Interrupt
269
270/**
271 * @ingroup Common_register_group_W5100S
272 * @brief Socket Interrupt Mask Register(R/W)
273 * @details Each bit of \ref _IMR_ corresponds to each bit of \ref IR.
274 * When a bit of \ref _IMR_ is and the corresponding bit of \ref IR is set, Interrupt will be issued.
275 */
276#define _IMR_                           (_W5100S_IO_BASE_ + (0x0016)) // Socket Interrupt Mask
277
278/**
279 * @ingroup Common_register_group_W5100S
280 * @brief Timeout register address( 1 is 100us )(R/W)
281 * @details \ref _RTR_ configures the retransmission timeout period. The unit of timeout period is 100us and the default of \ref _RTR_ is x07D0or 000
282 * And so the default timeout period is 200ms(100us X 2000). During the time configured by \ref _RTR_, W5100S waits for the peer response
283 * to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
284 * If the peer does not respond within the \ref _RTR_ time, W5100S retransmits the packet or issues timeout.
285 */
286#define _RTR_                           (_W5100S_IO_BASE_ + (0x0017)) // Retry Time
287
288/**
289 * @ingroup Common_register_group_W5100S
290 * @brief Retry count register(R/W)
291 * @details \ref _RCR_ configures the number of time of retransmission.
292 * When retransmission occurs as many as ref _RCR_+1 Timeout interrupt is issued (\ref Sn_IR_TIMEOUT = '1').
293 */
294#define _RCR_                           (_W5100S_IO_BASE_ + (0x0019)) // Retry Count
295
296/**
297 * @ingroup Common_register_group_W5100S
298 * @brief Receive Memory Size Register
299 * @details \ref RMSR register configures RX bufffer Size of the SOCKET
300 * The sum of the RX buffers can not exceed 8kB.
301 * <table>
302 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
303 *              <tr>  <td>S3-1</td> <td>S3-0</td> <td>S2-1</td> <td>S2-0</td> <td>S1-1</td> <td>S1-0</td> <td>S0-1</td> <td>S0-0</td> </tr>
304 * </table>
305 * <table>
306 *              <tr> <td>Memory Size</td><td>Sn-1</td><td>Sn-0</td> </tr>
307 *              <tr> <td>1KB</td><td>0</td><td>0</td> </tr>
308 *              <tr> <td>2KB</td><td>0</td><td>1</td> </tr>
309 *              <tr> <td>4KB</td><td>1</td><td>0</td> </tr>
310 *              <tr> <td>8KB</td><td>1</td><td>1</td> </tr>
311 * </table>
312 */
313#define RMSR                            (_W5100S_IO_BASE_ + (0x001A)) // Receive Memory Size
314
315/**
316 * @ingroup Common_register_group_W5100S
317 * @brief Transmit Memory Size Register
318 * @details \ref TMSR register configures TX bufffer Size of the SOCKET
319 * The sum of the TX buffers can not exceed 8kB.
320 * <table>
321 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
322 *              <tr>  <td>S3-1</td> <td>S3-0</td> <td>S2-1</td> <td>S2-0</td> <td>S1-1</td> <td>S1-0</td> <td>S0-1</td> <td>S0-0</td> </tr>
323 * </table>
324 * <table>
325 *              <tr> <td>Memory Size</td><td>Sn-1</td><td>Sn-0</td> </tr>
326 *              <tr> <td>1KB</td><td>0</td><td>0</td> </tr>
327 *              <tr> <td>2KB</td><td>0</td><td>1</td> </tr>
328 *              <tr> <td>4KB</td><td>1</td><td>0</td> </tr>
329 *              <tr> <td>8KB</td><td>1</td><td>1</td> </tr>
330 * </table>
331 */
332#define TMSR                            (_W5100S_IO_BASE_ + (0x001B)) // Transmit Memory Size
333
334/**
335 * @ingroup Common_register_group_W5100S
336 * @brief Interrupt register 2
337 * @details \ref IR2 indicates the interrupt status.
338 * Each bit of IR2 will be still until the bit will be written to by the host.
339 * <table>
340 *              <tr>  <td>7:1</td> <td>0</td>   </tr>
341 *              <tr>  <td>Reserved</td> <td>WOL</td> </tr>
342 * </table>
343 * - \ref IR2_WOL : WOL MAGIC PACKET Interrupt Mask
344 */
345#define IR2                                     (_W5100S_IO_BASE_ + (0x0020))
346
347/**
348 * @ingroup Common_register_group_W5100S
349 * @brief Interrupt mask register 2
350 * @details \ref IMR2 Each bit of IMR2 corresponds to each bit of IR2.
351 * When a bit of IMR2 is and the corresponding bit of IR2 is set, Interrupt will be issued.
352 */
353#define IMR2                            (_W5100S_IO_BASE_ + (0x0021))
354
355
356/**
357 * @ingroup Common_register_group_W5100S
358 * @brief PPP LCP Request Timer register  in PPPoE mode(R)
359 * @details \ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
360 */
361#define PTIMER                          (_W5100S_IO_BASE_ + (0x0028)) // PPP LCP RequestTimer
362
363/**
364 * @ingroup Common_register_group_W5100S
365 * @brief PPP LCP Magic number register  in PPPoE mode(R)
366 * @details \ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
367 */
368#define PMAGIC                          (_W5100S_IO_BASE_ + (0x0029)) // PPP LCP Magic number
369
370/**
371 * @ingroup Common_register_group_W5100S
372 * @brief Unreachable IP address register
373 * @details \ref
374 */
375#define UIPR                            (_W5100S_IO_BASE_ + (0x002A))
376
377/**
378 * @ingroup Common_register_group_W5100S
379 * @brief Unreachable Port register
380 * @details \ref
381 */
382#define UPORTR                          (_W5100S_IO_BASE_  + (0x002E))
383
384/* register for W5100S only */
385
386/*------------------------------------------ Common registers ------------------------------------------*/
387
388/**
389 * @ingroup Common_register_group_W5100S
390 * @brief MR2 Mode register 2
391 * @details \reg
392 */
393#define MR2                                     (_W5100S_IO_BASE_ + (0x0030))
394
395
396/**
397 * @ingroup Common_register_group_W5100S
398 * @brief Destination Hardware address in PPPoE
399 * @details \reg
400 */
401#define PHAR                            (_W5100S_IO_BASE_ + (0x0032))
402
403/**
404 * @ingroup Common_register_group_W5100S
405 * @brief Session ID in PPPoE
406 * @details \reg
407 */
408#define PSIDR                           (_W5100S_IO_BASE_ + (0x0038))
409
410/**
411 * @ingroup Common_register_group_W5100S
412 * @brief Maximum receive Unit in PPPoE
413 * @details \reg
414 */
415#define PMRUR                           (_W5100S_IO_BASE_ + (0x003A))
416
417
418/*------------------------------------------ PHY registers ------------------------------------------*/
419
420/**
421 * @ingroup Common_register_group_W5100S
422 * @brief PHY status register
423 * @details \reg
424 */
425#define PHYSR                           (_W5100S_IO_BASE_ + (0x003C))
426
427/**
428 * @ingroup Common_register_group_W5100S
429 * @brief PHY status register(hidden)
430 * @details \reg
431 */
432#define PHYSR1                          (_W5100S_IO_BASE_ + (0x003D))
433
434/**
435 * @ingroup Common_register_group_W5100S
436 * @brief PHY Address value
437 * @details \reg
438 */
439#define PHYAR                           (_W5100S_IO_BASE_ + (0x003E))
440
441/**
442 * @ingroup Common_register_group_W5100S
443 * @brief PHY Register address
444 * @details \reg
445 */
446#define PHYRAR                          (_W5100S_IO_BASE_ + (0x003F))
447
448/**
449 * @ingroup Common_register_group_W5100S
450 * @brief PHY Data input register
451 * @details \reg
452 */
453#define PHYDIR                          (_W5100S_IO_BASE_ + (0x0040))
454
455/**
456 * @ingroup Common_register_group_W5100S
457 * @brief PHY data output register
458 * @details \reg
459 */
460#define PHYDOR                          (_W5100S_IO_BASE_ + (0x0042))
461
462/**
463 * @ingroup Common_register_group_W5100S
464 * @brief PHY Action register
465 * @details \reg
466 */
467#define PHYACR                          (_W5100S_IO_BASE_ + (0x0044))
468
469/**
470 * @ingroup Common_register_group_W5100S
471 * @brief PHY Division register
472 * @details \reg
473 */
474#define PHYDIVR                         (_W5100S_IO_BASE_ + (0x0045))
475
476/**
477 * @ingroup Common_register_group_W5100S
478 * @brief PHY Control register 0
479 * @details \reg
480 */
481#define PHYCR0                                  (_W5100S_IO_BASE_ + (0x0046))
482/**
483 * @ingroup Common_register_group_W5100S
484 * @brief PHY Control register 1
485 * @details \reg
486 */
487#define PHYCR1                                  (_W5100S_IO_BASE_ + (0x0047))
488
489/*------------------------------------------ Socket Less registers ------------------------------------------*/
490
491/**
492 * @ingroup Common_register_group_W5100S
493 * @brief Socket-less control register
494 * @details \reg
495 */
496#define SLCR                            (_W5100S_IO_BASE_ + (0x004C))
497
498/**
499 * @ingroup Common_register_group_W5100S
500 * @brief Socket-less retry time register
501 * @details \reg
502 */
503#define SLRTR                           (_W5100S_IO_BASE_ + (0x004D))
504
505
506/**
507 * @ingroup Common_register_group_W5100S
508 * @brief Socket-less retry count register
509 * @details \reg
510 */
511#define SLRCR                           (_W5100S_IO_BASE_ + (0x004F))
512
513/**
514 * @ingroup Common_register_group_W5100S
515 * @brief Socket-less peer IP address register
516 * @details \reg
517 */
518#define SLPIPR                          (_W5100S_IO_BASE_ + (0x0050))
519
520/**
521 * @ingroup Common_register_group_W5100S
522 * @brief Socket-less peer hardware address register
523 * @details \reg
524 */
525#define SLPHAR                          (_W5100S_IO_BASE_ + (0x0054))
526
527/**
528 * @ingroup Common_register_group_W5100S
529 * @brief Ping sequence number register
530 * @details \reg
531 */
532#define PINGSEQR                                (_W5100S_IO_BASE_ + (0x005A))
533
534/**
535 * @ingroup Common_register_group_W5100S
536 * @brief Ping ID register
537 * @details \reg
538 */
539#define PINGIDR                         (_W5100S_IO_BASE_ + (0x005C))
540
541/**
542 * @ingroup Common_register_group_W5100S
543 * @brief Socket-less interrupt mask register
544 * @details \reg
545 */
546#define SLIMR                           (_W5100S_IO_BASE_ + (0x005E))
547
548/**
549 * @ingroup Common_register_group_W5100S
550 * @brief  Socket-less interrupt register
551 * @details \reg
552 */
553#define SLIR                            (_W5100S_IO_BASE_ + (0x005F))
554
555/**
556 * @ingroup Common_register_group_W5100S
557 * @brief DBGOUT(hidden)
558 * @details \reg
559 */
560#define DBGOUT                          (_W5100S_IO_BASE_ + (0x0060))
561
562/**
563 * @ingroup Common_register_group_W5100S
564 * @brief NICMAXCOLR(hidden)
565 * @details \reg
566 */
567#define NICMAXCOLR                      (_W5100S_IO_BASE_ + (0x0063))
568/*------------------------------------------ CFG registers ------------------------------------------*/
569
570/**
571 * @ingroup Common_register_group_W5100S
572 * @brief Chip Configuration locking register
573 * @details \reg
574 */
575#define CHIPLCKR                                (_W5100S_IO_BASE_ + (0x0070))
576
577/**
578 * @ingroup Common_register_group_W5100S
579 * @brief Network Configuration locking register
580 * @details \reg
581 */
582#define NETLCKR                         (_W5100S_IO_BASE_ + (0x0071))
583
584/**
585 * @ingroup Common_register_group_W5100S
586 * @brief PHY Configuration locking register
587 * @details \reg
588 */
589#define PHYLCKR                         (_W5100S_IO_BASE_ + (0x0072))
590
591/**
592 * @ingroup Common_register_group_W5100S
593 * @brief version register
594 * @details \reg
595 */
596#define VERR                            (_W5100S_IO_BASE_ + (0x0080))
597
598/**
599 * @ingroup Common_register_group_W5100S
600 * @brief Core 100us Counter register
601 * @details \reg
602 */
603#define TCNTR                           (_W5100S_IO_BASE_ + (0x0082))
604
605/**
606 * @ingroup Common_register_group_W5100S
607 * @brief Core 100us Counter clear register
608 * @details \reg
609 */
610#define TCNTCLKR                        (_W5100S_IO_BASE_ + (0x0088))
611
612//----------------------------- W5100S Socket Registers -----------------------------
613
614//--------------------------- For Backward Compatibility ---------------------------
615
616/**
617 * @ingroup Socket_register_group_W5100S
618 * @brief socket Mode register(R/W)
619 * @details \ref Sn_MR configures the option or protocol type of Socket n.\n\n
620 * Each bit of \ref Sn_MR defined as the following.
621 * <table>
622 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
623 *              <tr>  <td>MULTI</td> <td>MF</td> <td>ND/MC</td> <td>Reserved</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr>
624 * </table>
625 * - \ref Sn_MR_MULTI   : Support UDP Multicasting
626 * - \ref Sn_MR_MF         : Support MACRAW
627 * - \ref Sn_MR_ND              : No Delayed Ack(TCP) flag
628 * - \ref Sn_MR_MC      : IGMP version used <b>in UDP mulitcasting</b>
629 * - <b>Protocol</b>
630 * <table>
631 *              <tr>   <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td>   </tr>
632 *              <tr>   <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td>   </tr>
633 *              <tr>   <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td>   </tr>
634 *              <tr>   <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td>   </tr>
635 *              <tr>   <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td>   </tr>
636 * </table>
637 * - <b>In case of Socket 0</b>
638 *  <table>
639 *              <tr>   <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td>   </tr>
640 *              <tr>   <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td>   </tr>
641 *              <tr>   <td>0</td> <td>1</td> <td>0</td> <td>1</td> <td>PPPoE</td>   </tr>
642 * </table>
643 *       - \ref Sn_MR_MACRAW    : MAC LAYER RAW SOCK \n
644 *  - \ref Sn_MR_UDP            : UDP
645 *  - \ref Sn_MR_TCP            : TCP
646 *  - \ref Sn_MR_CLOSE  : Unused socket
647 *  @note MACRAW mode should be only used in Socket 0.
648 */
649#define Sn_MR(sn)                       (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000)) // socket Mode register
650
651/**
652 * @ingroup Socket_register_group_W5100S
653 * @brief Socket command register(R/W)
654 * @details This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.\n
655 * After W5100S accepts the command, the \ref Sn_CR register is automatically cleared to 0x00.
656 * Even though \ref Sn_CR is cleared to 0x00, the command is still being processed.\n
657 * To check whether the command is completed or not, please check the \ref Sn_IR or \ref Sn_SR.
658 * - \ref Sn_CR_OPEN            : Initialize or open socket.
659 * - \ref Sn_CR_LISTEN          : Wait connection request in TCP mode(<b>Server mode</b>)
660 * - \ref Sn_CR_CONNECT         : Send connection request in TCP mode(<b>Client mode</b>)
661 * - \ref Sn_CR_DISCON          : Send closing request in TCP mode.
662 * - \ref Sn_CR_CLOSE           : Close socket.
663 * - \ref Sn_CR_SEND            : Update TX buffer pointer and send data.
664 * - \ref Sn_CR_SEND_MAC        : Send data with MAC address, so without ARP process.
665 * - \ref Sn_CR_SEND_KEEP       : Send keep alive message.
666 * - \ref Sn_CR_RECV            : Update RX buffer pointer and receive data.
667 * - <b>In case of S0_MR(P3:P0) = S0_MR_PPPoE</b>
668 *  <table>
669 *              <tr>   <td><b>Value</b></td> <td><b>Symbol</b></td> <td><b>Description</b></td></tr>
670 *              <tr>   <td>0x23</td> <td>PCON</td> <td>PPPoE connection begins by transmitting PPPoE discovery packet</td>  </tr>
671 *              <tr>   <td>0x24</td> <td>PDISCON</td> <td>Closes PPPoE connection</td>  </tr>
672 *              <tr>   <td>0x25</td> <td>PCR</td> <td>In each phase, it transmits REQ message.</td> </tr>
673 *              <tr>   <td>0x26</td> <td>PCN</td> <td>In each phase, it transmits NAK message.</td> </tr>
674 *              <tr>   <td>0x27</td> <td>PCJ</td> <td>In each phase, it transmits REJECT message.</td> </tr>
675 * </table>
676 */
677#define Sn_CR(sn)                       (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001)) // channel Sn_CR register
678
679/**
680 * @ingroup Socket_register_group_W5100S
681 * @brief Socket interrupt register(R)
682 * @details \ref Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).\n
683 * When an interrupt occurs and the corresponding bit \ref IR_SOCK(N) in \ref _IMR_ are set, \ref IR_SOCK(N) in \ref IR becomes '1'.\n
684 * In order to clear the \ref Sn_IR bit, the host should write the bit to \n
685 * <table>
686 *              <tr>  <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td>   </tr>
687 *              <tr>  <td>PRECV</td> <td>PFAIL</td> <td>PNEXT</td> <td>SEND_OK</td> <td>TIMEOUT</td> <td>RECV</td> <td>DISCON</td> <td>CON</td> </tr>
688 * </table>
689 * - \ref Sn_IR_PRECV : <b>PPP Receive Interrupt</b>
690 * - \ref Sn_IR_PFAIL : <b>PPP Fail Interrupt</b>
691 * - \ref Sn_IR_PNEXT : <b>PPP Next Phase Interrupt</b>
692 * - \ref Sn_IR_SENDOK : <b>SEND_OK Interrupt</b>
693 * - \ref Sn_IR_TIMEOUT : <b>TIMEOUT Interrupt</b>
694 * - \ref Sn_IR_RECV : <b>RECV Interrupt</b>
695 * - \ref Sn_IR_DISCON : <b>DISCON Interrupt</b>
696 * - \ref Sn_IR_CON : <b>CON Interrupt</b>
697 */
698#define Sn_IR(sn)                       (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002)) // channel interrupt register
699
700/**
701 * @ingroup Socket_register_group_W5100S
702 * @brief Socket status register(R)
703 * @details \ref Sn_SR indicates the status of Socket n.\n
704 * The status of Socket n is changed by \ref Sn_CR or some special control packet as SYN, FIN packet in TCP.
705 * @par Normal status
706 * - \ref SOCK_CLOSED           : Closed
707 * - \ref SOCK_INIT             : Initiate state
708 * - \ref SOCK_LISTEN           : Listen state
709 * - \ref SOCK_ESTABLISHED      : Success to connect
710 * - \ref SOCK_CLOSE_WAIT   : Closing state
711 * - \ref SOCK_UDP              : UDP socket
712 * - \ref SOCK_MACRAW           : MAC raw mode socket
713 *@par Temporary status during changing the status of Socket n.
714 * - \ref SOCK_SYNSENT          : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
715 * - \ref SOCK_SYNRECV          : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
716 * - \ref SOCK_FIN_WAIT         : Connection state
717 * - \ref SOCK_CLOSING          : Closing state
718 * - \ref SOCK_TIME_WAIT        : Closing state
719 * - \ref SOCK_LAST_ACK         : Closing state
720 */
721#define Sn_SR(sn)                       (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003)) // channel status register
722
723/**
724 * @ingroup Socket_register_group_W5100S
725 * @brief source port register(R/W)
726 * @details \ref Sn_PORT configures the source port number of Socket n.
727 * It is valid when Socket n is used in TCP/UDP mode. It should be set before OPEN command is ordered.
728*/
729#define Sn_PORT(sn)             (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004)) // source port register
730
731/**
732 * @ingroup Socket_register_group_W5100S
733 * @brief Peer MAC register address(R/W)
734 * @details \ref Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or
735 * it indicates that it is acquired in ARP-process by CONNECT/SEND command.
736 */
737#define Sn_DHAR(sn)     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006)) // Peer MAC register address
738
739/**
740 * @ingroup Socket_register_group_W5100S
741 * @brief Peer IP register address(R/W)
742 * @details \ref Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode.
743 * In TCP client mode, it configures an IP address of TCP server before CONNECT command.
744 * In TCP server mode, it indicates an IP address of TCP client after successfully establishing connection.
745 * In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.
746 */
747#define Sn_DIPR(sn)             (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C)) // Peer IP register address
748
749/**
750 * @ingroup Socket_register_group_W5100S
751 * @brief Peer port register address(R/W)
752 * @details \ref Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode.
753 * In TCP clientmode, it configures the listen port number of TCP server before CONNECT command.
754 * In TCP Servermode, it indicates the port number of TCP client after successfully establishing connection.
755 * In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.
756 */
757#define Sn_DPORT(sn)    (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010)) // Peer port register address
758
759/**
760 * @ingroup Socket_register_group_W5100S
761 * @brief Maximum Segment Size(Sn_MSSR0) register address(R/W)
762 * @details \ref Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.
763 */
764#define Sn_MSSR(sn)        (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012)) // Maximum Segment Size(Sn_MSSR0) register address
765
766/**
767 * @ingroup Socket_register_group_W5100S
768 * @brief IP Protocol(PROTO) Register(R/W)
769 * @details \ref Sn_PROTO that sets the protocol number field of the IP header at the IP layer. It is
770 * valid only in IPRAW mode, and ignored in other modes.
771 */
772#define Sn_PROTO(sn)       (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014)) // Protocol of IP Header field register in IP raw mode
773
774/**
775 * @ingroup Socket_register_group_W5100S
776 * @brief IP Type of Service(TOS) Register(R/W)
777 * @details \ref Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n.
778 * It is set before OPEN command.
779 */
780#define Sn_TOS(sn)                      (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + 0x0015) // IP Type of Service(TOS) Register
781
782/**
783 * @ingroup Socket_register_group_W5100S
784 * @brief IP Time to live(TTL) Register(R/W)
785 * @details \ref Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n.
786 * It is set before OPEN command.
787 */
788#define Sn_TTL(sn)              (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016)) // IP Time to live(TTL) Register
789
790// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0017))
791// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0018))
792// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0019))
793// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001A))
794// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001B))
795// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001C))
796// Reserved                                     (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001D))
797
798
799
800/**
801 * @ingroup Socket_register_group_W5100S
802 * @brief Receive memory size register(R/W)
803 * @details @ref Sn_RXBUF_SIZE configures the RX buffer block size of Socket n.
804 * Socket n RX Buffer Block size can be configured with 1,2,4 and 8Kbytes.
805 * If a different size is configured, the data cannot be normally received from a peer.
806 * Although Socket n RX Buffer Block size is initially configured to 2Kbytes,
807 * user can re-configure its size using @ref Sn_RXBUF_SIZE. The total sum of @ref Sn_RXBUF_SIZE can not be exceed 8Kbytes.
808 * When exceeded, the data reception error is occurred.
809 */
810#define Sn_RXBUF_SIZE(sn)   (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E))
811
812/**
813 * @ingroup Socket_register_group_W5100S
814 * @brief Transmit memory size register(R/W)
815 * @details @ref Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4 and 8Kbytes.
816 * If a different size is configured, the data cannot be normally transmitted to a peer.
817 * Although Socket n TX Buffer Block size is initially configured to 2Kbytes,
818 * user can be re-configure its size using @ref Sn_TXBUF_SIZE. The total sum of @ref Sn_TXBUF_SIZE can not be exceed 8Kbytes.
819 * When exceeded, the data transmission error is occurred.
820 */
821#define Sn_TXBUF_SIZE(sn)   (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F))
822
823
824/**
825 * @ingroup Socket_register_group_W5100S
826 * @brief Transmit free memory size register(R)
827 * @details \ref Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by \ref Sn_TXMEM_SIZE.
828 * Data bigger than \ref Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent.
829 * Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size,
830 * transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size,
831 * transmit the data after dividing into the checked size and saving in the Socket n TX buffer.
832 */
833#define Sn_TX_FSR(sn)   (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020)) // Transmit free memory size register
834
835/**
836 * @ingroup Socket_register_group_W5100S
837 * @brief Transmit memory read pointer register address(R)
838 * @details \ref Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP.
839 * After its initialization, it is auto-increased by SEND command.
840 * SEND command transmits the saved data from the current \ref Sn_TX_RD to the \ref Sn_TX_WR in the Socket n TX Buffer.
841 * After transmitting the saved data, the SEND command increases the \ref Sn_TX_RD as same as the \ref Sn_TX_WR.
842 * If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
843 * then the carry bit is ignored and will automatically update with the lower 16bits value.
844 */
845#define Sn_TX_RD(sn)            (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022)) // Transmit memory read pointer register address
846
847/**
848 * @ingroup Socket_register_group_W5100S
849 * @brief Transmit memory write pointer register address(R/W)
850 * @details \ref Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP.\n
851 * It should be read or be updated like as follows.\n
852 * 1. Read the starting address for saving the transmitting data.\n
853 * 2. Save the transmitting data from the starting address of Socket n TX buffer.\n
854 * 3. After saving the transmitting data, update \ref Sn_TX_WR to the increased value as many as transmitting data size.
855 * If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs),
856 * then the carry bit is ignored and will automatically update with the lower 16bits value.\n
857 * 4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command
858 */
859#define Sn_TX_WR(sn)            (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024)) // Transmit memory write pointer register address
860
861/**
862 * @ingroup Socket_register_group_W5100S
863 * @brief Received data size register(R)
864 * @details \ref Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer.
865 * \ref Sn_RX_RSR does not exceed the \ref Sn_RXMEM_SIZE and is calculated as the difference between
866 * Socket n RX Write Pointer (\ref Sn_RX_WR)and Socket n RX Read Pointer (\ref Sn_RX_RD)
867 */
868#define Sn_RX_RSR(sn)   (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026)) // Received data size register
869
870/**
871 * @ingroup Socket_register_group_W5100S
872 * @brief Read point of Receive memory(R/W)
873 * @details \ref Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.\n
874 * 1. Read the starting save address of the received data.\n
875 * 2. Read data from the starting address of Socket n RX Buffer.\n
876 * 3. After reading the received data, Update \ref Sn_RX_RD to the increased value as many as the reading size.
877 * If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs,
878 * update with the lower 16bits value ignored the carry bit.\n
879 * 4. Order RECV command is for notifying the updated \ref Sn_RX_RD to W5100S.
880 */
881#define Sn_RX_RD(sn)            (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028)) // Read point of Receive memory
882
883/**
884 * @ingroup Socket_register_group_W5100S
885 * @brief Write point of Receive memory(R)
886 * @details \ref Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception.
887 * If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs),
888 * then the carry bit is ignored and will automatically update with the lower 16bits value.
889 */
890#define Sn_RX_WR(sn)            (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A)) // Write point of Receive memory
891
892
893//todo
894/**
895 * @ingroup Socket_register_group_W5100S
896 * @brief Socket interrupt mask register
897 * @details Register address to configure the interrupt mask of the socket
898 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
899 *
900 */
901#define Sn_IMR(sn)                      (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C))
902
903/**
904 * @ingroup Socket_register_group_W5100S
905 * @brief Socket fragment field register
906 * @details Register to configure the Fragment field of IP Header
907 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
908 */
909#define Sn_FRAGR(sn)            (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D)) // and +1
910
911/**
912 * @ingroup Socket_register_group_W5100S
913 * @brief Socket Mode register 2
914 * @details Register to set mode 2
915 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
916 */
917#define Sn_MR2(sn)                      (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002F))
918
919/**
920 * @ingroup Socket_register_group_W5100S
921 * @brief Socket n Keep Alive Timer Register
922 * @details Register to set the transmission period of keep alive packet.
923 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
924 */
925#define Sn_KPALVTR(sn)          (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0030))
926
927/** todo delete
928 * @ingroup Socket_register_group_W5100S
929 * @brief Socket n Timer Status Register
930 * @details
931 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
932 */
933//#define Sn_TSR(sn)                    (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0031))
934
935/**
936 * @ingroup Socket_register_group_W5100S
937 * @brief Socket n Retry Time-value Register
938 * @details Register to set the retry time value
939 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
940 */
941#define Sn_RTR(sn)                      (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0032))
942
943/**
944 * @ingroup Socket_register_group_W5100S
945 * @brief Socket n Retry Count-value Register
946 * @details Register to set the retry count value
947 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
948 */
949#define Sn_RCR(sn)                      (_W5100S_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0034))
950
951
952/*----------------------------- W5100S Register values  -----------------------------*/
953
954/* MODE register values */
955/**
956 * @brief Reset
957 * @details If this bit is  All internal registers will be initialized. It will be automatically cleared as after S/W reset.
958 */
959#define MR_RST                          0x80 ///< reset
960
961
962/**
963 * @brief Ping block
964 * @details 0 : Disable Ping block\n
965 * 1 : Enable Ping block\n
966 * If the bit is  it blocks the response to a ping request.
967 */
968#define MR_PB                           0x10 ///< ping block
969
970/**
971 * @brief Enable PPPoE
972 * @details 0 : DisablePPPoE mode\n
973 * 1 : EnablePPPoE mode\n
974 * If you use ADSL, this bit should be '1'.
975 */
976#define MR_PPPOE                        0x08 ///< enable pppoe
977
978/**
979 * @brief Address Auto-Increment in Indirect Bus Interface
980 * @details 0 : Disable auto-increment \n
981 * 1 : Enable auto-incremente \n
982 * At the Indirect Bus Interface mode, if this bit is set as the address will
983 * be automatically increased by 1 whenever read and write are performed.
984 */
985#define MR_AI                           0x02 ///< auto-increment in indirect mode
986
987/**
988 * @brief Indirect Bus Interface mode
989 * @details 0 : Disable Indirect bus Interface mode \n
990 * 1 : Enable Indirect bus Interface mode \n
991 * If this bit is set as Indirect Bus Interface mode is set.
992 */
993#define MR_IND                          0x01 ///< enable indirect mode
994
995/* IR register values */
996/**
997 * @brief Check IP conflict.
998 * @details Bit is set as when own source IP address is same with the sender IP address in the received ARP request.
999 */
1000#define IR_CONFLICT                     0x80 ///< check ip confict
1001
1002/**
1003 * @brief Get the destination unreachable message in UDP sending.
1004 * @details When receiving the ICMP (Destination port unreachable) packet, this bit is set as
1005 * When this bit is  Destination Information such as IP address and Port number may be checked with the corresponding @ref UIPR & @ref UPORTR.
1006 */
1007#define IR_UNREACH                      0x40 ///< check destination unreachable
1008
1009/**
1010 * @brief Get the PPPoE close message.
1011 * @details When PPPoE is disconnected during PPPoE mode, this bit is set.
1012 */
1013#define IR_PPPoE                        0x20 ///< get the PPPoE close message
1014
1015/**
1016 * @brief Socket interrupt bit
1017 * @details Indicates whether each socket interrupt has occured.
1018 */
1019#define IR_SOCK(sn)             (0x01 << sn)    ///< check socket interrupt
1020
1021/**
1022 * @brief IP conflict interrupt mask bit
1023 * @details If this bit is set, IP conflict interrupt is enabled.
1024 */
1025#define IMR_CONFLICT            0x80
1026
1027/**
1028 * @brief Destination port unreachable interrupt mask bit
1029 * @details If this bit is set, destination port unreachable interrupt is enabled.
1030 */
1031#define IMR_UNREACH                     0x40
1032
1033/**
1034 * @brief PADT/LCPT interrupt mask bit(PPPoE)
1035 * @details If this bit is set, PADT/LCPT interrupt is enabled.
1036 */
1037#define IMR_PPPoE                       0x20
1038
1039/**
1040 * @brief Socket interrupt mask bit
1041 * @details If this bit is set, each socket interrupt is enabled.
1042 */
1043#define IMR_SOCK(sn)            (0x01 << sn)
1044
1045/**
1046 * @brief Socket-less command register bit
1047 * @details ARP command
1048 */
1049#define SLCMD_ARP               (1<<1)
1050
1051/**
1052 * @brief Socket-less command register bit
1053 * @details ARP command
1054 */
1055#define SLCMD_PING              (1<<0)
1056
1057/**
1058 * @brief Socket-less command interrupt and interrupt mask register bit
1059 * @details Request command time out interrupt and interrupt mask
1060 */
1061#define SLIR_TIMEOUT            (1<<2)
1062
1063/**
1064* @brief Socket less command interrupt and interrupt mask register bit
1065* @details Socket less command ARP interrupt and interrupt mask
1066*/
1067#define SLIR_ARP (1<<1)
1068
1069/**
1070* @brief Socket less command interrupt and interrupt mask register bit
1071* @details Socket less command PING interrupt and interruptmask
1072*/
1073#define SLIR_PING (1<<0)
1074
1075
1076
1077// Sn_MR values
1078/* Sn_MR Default values */
1079/**
1080 * @brief Unused socket
1081 * @details This configures the protocol mode of Socket n.
1082 */
1083#define Sn_MR_CLOSE                     0x00 ///< unused socket
1084
1085/**
1086 * @brief TCP
1087 * @details This configures the protocol mode of Socket n.
1088 */
1089#define Sn_MR_TCP                       0x01 ///< TCP
1090
1091/**
1092 * @brief UDP
1093 * @details This configures the protocol mode of Socket n.
1094 */
1095#define Sn_MR_UDP       0x02 ///< UDP
1096#define Sn_MR_IPRAW     0x03 ///< IP LAYER RAW SOCK
1097
1098/**
1099 * @brief MAC LAYER RAW SOCK
1100 * @details This configures the protocol mode of Socket n.
1101 * @note MACRAW mode should be only used in Socket 0.
1102 */
1103#define Sn_MR_MACRAW            0x04 ///< MAC LAYER RAW SOCK
1104
1105/**
1106 * @brief PPPoE
1107 * @details This configures the protocol mode of Socket n.
1108 * @note PPPoE mode should be only used in Socket 0.
1109 */
1110#define Sn_MR_PPPoE                     0x05 ///< PPPoE
1111
1112/**
1113 * @brief No Delayed Ack(TCP), Multicast flag
1114 * @details 0 : Disable No Delayed ACK option\n
1115 * 1 : Enable No Delayed ACK option\n
1116 * This bit is applied only during TCP mode (P[3:0] = 001).\n
1117 * When this bit is  It sends the ACK packet without delay as soon as a Data packet is received from a peer.\n
1118 * When this bit is  It sends the ACK packet after waiting for the timeout time configured by \ref _RTR_.
1119 */
1120#define Sn_MR_ND                        0x20 ///< No Delayed Ack(TCP) flag
1121
1122/**
1123 * @brief Support UDP Multicasting
1124 * @details 0 : using IGMP version 2\n
1125 * 1 : using IGMP version 1\n
1126 * This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = '1')
1127 * It configures the version for IGMP messages (Join/Leave/Report).
1128 */
1129#define Sn_MR_MC                        Sn_MR_ND ///< Select IGMP version 1(0) or 2(1)
1130
1131/**
1132 * @brief MAC filter enable in @ref Sn_MR_MACRAW mode
1133 * @details 0 : disable MAC Filtering\n
1134 * 1 : enable MAC Filtering\n
1135 * This bit is applied only during MACRAW mode(P[3:0] = 100.\n
1136 * When set as  W5100S can only receive broadcasting packet or packet sent to itself.
1137 * When this bit is  W5100S can receive all packets on Ethernet.
1138 * If user wants to implement Hybrid TCP/IP stack,
1139 * it is recommended that this bit is set as for reducing host overhead to process the all received packets.
1140 */
1141#define Sn_MR_MF                        0x40 ///< Use MAC filter
1142#define Sn_MR_MFEN      Sn_MR_MF
1143
1144
1145/* Sn_MR Default values */
1146/**
1147 * @brief Support UDP Multicasting
1148 * @details 0 : disable Multicasting\n
1149 * 1 : enable Multicasting\n
1150 * This bit is applied only during UDP mode(P[3:0] = 010).\n
1151 * To use multicasting, \ref Sn_DIPR & \ref Sn_DPORT should be respectively configured with the multicast group IP address & port number
1152 * before Socket n is opened by OPEN command of \ref Sn_CR.
1153 */
1154#define Sn_MR_MULTI                     0x80 ///< support multicating
1155
1156/* Sn_CR values */
1157/**
1158 * @brief Initialize or open socket
1159 * @details Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0).
1160 * The table below shows the value of \ref Sn_SR corresponding to \ref Sn_MR.\n
1161 * <table>
1162 *   <tr>  <td>\b Sn_MR (P[3:0])</td> <td>\b Sn_SR</td>                          </tr>
1163 *   <tr>  <td>Sn_MR_CLOSE  (000)</td> <td>--</td>                               </tr>
1164 *   <tr>  <td>Sn_MR_TCP  (001)</td> <td>SOCK_INIT (0x13)</td>                   </tr>
1165 *   <tr>  <td>Sn_MR_UDP  (010)</td>  <td>SOCK_UDP (0x22)</td>                   </tr>
1166 *   <tr>  <td>S0_MR_IPRAW  (011)</td>  <td>SOCK_IPRAW (0x32)</td>  </tr>
1167 *   <tr>  <td>S0_MR_MACRAW  (100)</td>  <td>SOCK_MACRAW (0x42)</td>  </tr>
1168 *   <tr>  <td>S0_MR_PPPoE  (101)</td>  <td>SOCK_PPPoE (0x5F)</td>  </tr>
1169 * </table>
1170 */
1171#define Sn_CR_OPEN                      0x01 ///< initialize or open socket
1172
1173/**
1174 * @brief Wait connection request in TCP mode(Server mode)
1175 * @details This is valid only in TCP mode (Sn_MR(P3:P0) = \ref Sn_MR_TCP).//
1176 * In this mode, Socket n operates as a 'TCP server' and waits for connection-request (SYN packet) from any 'TCP client'.//
1177 * The \ref Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.//
1178 * When a 'TCP client' connection request is successfully established,
1179 * the \ref Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes
1180 * But when a 'TCP client' connection request is failed, Sn_IR(3) becomes and the status of \ref Sn_SR changes to SOCK_CLOSED.
1181 */
1182#define Sn_CR_LISTEN            0x02 ///< wait connection request in tcp mode(Server mode)
1183
1184/**
1185 * @brief Send connection request in TCP mode(Client mode)
1186 * @details  To connect, a connect-request (SYN packet) is sent to <b>TCP server</b>configured by \ref Sn_DIPR & Sn_DPORT(destination address & port).
1187 * If the connect-request is successful, the \ref Sn_SR is changed to \ref SOCK_ESTABLISHED and the Sn_IR(0) becomes \n\n
1188 * The connect-request fails in the following three cases.\n
1189 * 1. When a @b ARPTO occurs (\ref Sn_IR[3] = '1') because destination hardware address is not acquired through the ARP-process.\n
1190 * 2. When a @b SYN/ACK packet is not received and @b TCPTO (Sn_IR(3) ='1')\n
1191 * 3. When a @b RST packet is received instead of a @b SYN/ACK packet. In these cases, \ref Sn_SR is changed to \ref SOCK_CLOSED.
1192 * @note This is valid only in TCP mode and operates when Socket n acts as <b>TCP client</b>
1193 */
1194#define Sn_CR_CONNECT           0x04 ///< send connection request in tcp mode(Client mode)
1195
1196/**
1197 * @brief Send closing request in TCP mode
1198 * @details Regardless of <b>TCP server</b>or <b>TCP client</b> the DISCON command processes the disconnect-process (<b>Active close</b>or <b>Passive close</b>.\n
1199 * @par Active close
1200 * it transmits disconnect-request(FIN packet) to the connected peer\n
1201 * @par Passive close
1202 * When FIN packet is received from peer, a FIN packet is replied back to the peer.\n
1203 * @details When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), \ref Sn_SR is changed to \ref SOCK_CLOSED.\n
1204 * Otherwise, TCPTO occurs (Sn_IR(3)='1') and then \ref Sn_SR is changed to \ref SOCK_CLOSED.
1205 * @note Valid only in TCP mode.
1206 */
1207#define Sn_CR_DISCON            0x08 ///< send closing reqeuset in tcp mode
1208
1209/**
1210 * @brief Close socket
1211 * @details Sn_SR is changed to \ref SOCK_CLOSED.
1212 */
1213#define Sn_CR_CLOSE         0x10
1214
1215/**
1216 * @brief Update TX buffer pointer and send data
1217 * @details SEND transmits all the data in the Socket n TX buffer.\n
1218 * For more details, please refer to Socket n TX Free Size Register (\ref Sn_TX_FSR), Socket n,
1219 * TX Write Pointer Register(\ref Sn_TX_WR), and Socket n TX Read Pointer Register(\ref Sn_TX_RD).
1220 */
1221#define Sn_CR_SEND          0x20
1222
1223/**
1224 * @brief Send data with MAC address, so without ARP process
1225 * @details The basic operation is same as SEND.\n
1226 * Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).\n
1227 * But SEND_MAC transmits data without the automatic ARP-process.\n
1228 * In this case, the destination hardware address is acquired from \ref Sn_DHAR configured by host, instead of APR-process.
1229 * @note Valid only in UDP mode.
1230 */
1231#define Sn_CR_SEND_MAC      0x21
1232
1233/**
1234 * @brief Send keep alive message
1235 * @details It checks the connection status by sending 1byte keep-alive packet.\n
1236 * If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.
1237 * @note Valid only in TCP mode.
1238 */
1239#define Sn_CR_SEND_KEEP     0x22
1240
1241/**
1242 * @brief Update RX buffer pointer and receive data
1243 * @details RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (\ref Sn_RX_RD).\n
1244 * For more details, refer to Socket n RX Received Size Register (\ref Sn_RX_RSR), Socket n RX Write Pointer Register (\ref Sn_RX_WR),
1245 * and Socket n RX Read Pointer Register (\ref Sn_RX_RD).
1246 */
1247#define Sn_CR_RECV          0x40
1248
1249/**
1250 * @brief
1251 * @details
1252 */
1253#define Sn_CR_IGMP_JOIN                 0x23
1254
1255/**
1256 * @brief
1257 * @details
1258 */
1259#define Sn_CR_IGMP_LEAVE                0x24
1260
1261
1262/* Sn_IR values */
1263
1264/**
1265 * @brief SEND_OK Interrupt
1266 * @details This is issued when SEND command is completed.
1267 */
1268#define Sn_IR_SENDOK            0x10 ///< complete sending
1269
1270/**
1271 * @brief TIMEOUT Interrupt
1272 * @details This is issued when ARPTO or TCPTO occurs.
1273 */
1274#define Sn_IR_TIMEOUT           0x08 ///< assert timeout
1275
1276/**
1277 * @brief RECV Interrupt
1278 * @details This is issued whenever data is received from a peer.
1279 */
1280#define Sn_IR_RECV          0x04
1281
1282/**
1283 * @brief DISCON Interrupt
1284 * @details This is issued when FIN or FIN/ACK packet is received from a peer.
1285 */
1286#define Sn_IR_DISCON        0x02
1287
1288/**
1289 * @brief CON Interrupt
1290 * @details This is issued one time when the connection with peer is successful and then \ref Sn_SR is changed to \ref SOCK_ESTABLISHED.
1291 */
1292#define Sn_IR_CON           0x01
1293
1294/* Sn_SR values */
1295/**
1296 * @brief Closed
1297 * @details This indicates that Socket n is released.\n
1298 * When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to \ref SOCK_CLOSED regardless of previous status.
1299 */
1300#define SOCK_CLOSED                     0x00 ///< closed
1301
1302/**
1303 * @brief Initiate state
1304 * @details This indicates Socket n is opened with TCP mode.\n
1305 * It is changed to \ref SOCK_INIT when Sn_MR(P[3:0]) = 001)and OPEN command is ordered.\n
1306 * After \ref SOCK_INIT, user can use LISTEN /CONNECT command.
1307 */
1308#define SOCK_INIT                       0x13 ///< init state
1309
1310/**
1311 * @brief Listen state
1312 * @details This indicates Socket n is operating as <b>TCP server</b>mode and waiting for connection-request (SYN packet) from a peer (<b>TCP client</b>).\n
1313 * It will change to \ref SOCK_ESTABLISHED when the connection-request is successfully accepted.\n
1314 * Otherwise it will change to \ref SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = '1').
1315 */
1316#define SOCK_LISTEN         0x14
1317
1318/**
1319 * @brief Connection state
1320 * @details This indicates Socket n sent the connect-request packet (SYN packet) to a peer.\n
1321 * It is temporarily shown when \ref Sn_SR is changed from \ref SOCK_INIT to \ref SOCK_ESTABLISHED by CONNECT command.\n
1322 * If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to \ref SOCK_ESTABLISHED.\n
1323 * Otherwise, it changes to \ref SOCK_CLOSED after TCPTO (\ref Sn_IR[TIMEOUT] = '1') is occurred.
1324 */
1325#define SOCK_SYNSENT        0x15
1326
1327/**
1328 * @brief Connection state
1329 * @details It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.\n
1330 * If socket n sends the response (SYN/ACK  packet) to the peer successfully,  it changes to \ref SOCK_ESTABLISHED. \n
1331 * If not, it changes to \ref SOCK_CLOSED after timeout occurs (\ref Sn_IR[TIMEOUT] = '1').
1332 */
1333#define SOCK_SYNRECV        0x16
1334
1335/**
1336 * @brief Success to connect
1337 * @details This indicates the status of the connection of Socket n.\n
1338 * It changes to \ref SOCK_ESTABLISHED when the <b>TCP SERVER</b>processed the SYN packet from the <b>TCP CLIENT</b>during \ref SOCK_LISTEN, or
1339 * when the CONNECT command is successful.\n
1340 * During \ref SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.
1341 */
1342#define SOCK_ESTABLISHED    0x17
1343
1344/**
1345 * @brief Closing state
1346 * @details These indicate Socket n is closing.\n
1347 * These are shown in disconnect-process such as active-close and passive-close.\n
1348 * When Disconnect-process is successfully completed, or when timeout occurs, these change to \ref SOCK_CLOSED.
1349 */
1350#define SOCK_FIN_WAIT       0x18
1351
1352/**
1353 * @brief Closing state
1354 * @details These indicate Socket n is closing.\n
1355 * These are shown in disconnect-process such as active-close and passive-close.\n
1356 * When Disconnect-process is successfully completed, or when timeout occurs, these change to \ref SOCK_CLOSED.
1357 */
1358#define SOCK_CLOSING        0x1A
1359
1360/**
1361 * @brief Closing state
1362 * @details These indicate Socket n is closing.\n
1363 * These are shown in disconnect-process such as active-close and passive-close.\n
1364 * When Disconnect-process is successfully completed, or when timeout occurs, these change to \ref SOCK_CLOSED.
1365 */
1366#define SOCK_TIME_WAIT      0x1B
1367
1368/**
1369 * @brief Closing state
1370 * @details This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.\n
1371 * This is half-closing status, and data can be transferred.\n
1372 * For full-closing, DISCON command is used. But For just-closing, @ref Sn_CR_CLOSE command is used.
1373 */
1374#define SOCK_CLOSE_WAIT     0x1C
1375
1376/**
1377 * @brief Closing state
1378 * @details This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.\n
1379 * It changes to \ref SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs  (\ref Sn_IR[TIMEOUT] = '1').
1380 */
1381#define SOCK_LAST_ACK       0x1D
1382
1383/**
1384 * @brief UDP socket
1385 * @details This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010).\n
1386 * It changes to SOCK_UDP when Sn_MR(P[3:0]) = 010 and @ref Sn_CR_OPEN command is ordered.\n
1387 * Unlike TCP mode, data can be transfered without the connection-process.
1388 */
1389#define SOCK_UDP                        0x22 ///< udp socket
1390
1391/**
1392 * @brief IP raw mode socket
1393 * @details TThe socket is opened in IPRAW mode. The SOCKET status is change to SOCK_IPRAW when @ref Sn_MR (P3:P0) is
1394 * Sn_MR_IPRAW and @ref Sn_CR_OPEN command is used.\n
1395 * IP Packet can be transferred without a connection similar to the UDP mode.
1396*/
1397#define SOCK_IPRAW                      0x32 ///< ip raw mode socket
1398
1399/**
1400 * @brief MAC raw mode socket
1401 * @details This indicates Socket 0 is opened in MACRAW mode (@ref Sn_MR(P[3:0]) = '100' and n=0) and is valid only in Socket 0.\n
1402 * It changes to SOCK_MACRAW when @ref Sn_MR(P[3:0]) = '100' and @ref Sn_CR_OPEN command is ordered.\n
1403 * Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.
1404 */
1405#define SOCK_MACRAW                     0x42 ///< mac raw mode socket
1406
1407/**
1408 * @brief PPPoE mode socket
1409 * @details It is the status that SOCKET0 is open as PPPoE mode. It is changed to SOCK_PPPoE in case of S0_CR=OPEN and S0_MR
1410 * (P3:P0)=S0_MR_PPPoE.\n
1411 * It is temporarily used at the PPPoE
1412connection.
1413 */
1414#define SOCK_PPPOE                      0x5F ///< pppoe socket
1415
1416// IP PROTOCOL
1417#define IPPROTO_IP                      0 ///< Dummy for IP
1418#define IPPROTO_ICMP               1 ///< Control message protocol
1419#define IPPROTO_IGMP               2 ///< Internet group management protocol
1420#define IPPROTO_GGP                     3 ///< GW^2 (deprecated)
1421#define IPPROTO_TCP                     6 ///< TCP
1422#define IPPROTO_PUP                     12 ///< PUP
1423#define IPPROTO_UDP                     17 ///< UDP
1424#define IPPROTO_IDP                     22 ///< XNS idp
1425#define IPPROTO_ND                      77 ///< UNOFFICIAL net disk protocol
1426#define IPPROTO_RAW                     255 ///< Raw IP packet
1427
1428
1429
1430/*----------------------------- W5100S !!Only!! Register values  -----------------------------*/
1431
1432//todo
1433/* MODE2 register values */
1434
1435/**
1436 * @brief       Clock select bit
1437 * @details     With this bit, system clock can be selected to be 25Mhz or 100Mhz
1438 * 1: 25Mhz
1439 * 0: 100Mhz (default)
1440 */
1441#define MR2_CLKSEL                              (1<<7)
1442
1443/**
1444 * @brief       Interrupt pin enable bit
1445 * @details     This bit enables interrupt.
1446 * 1: Enable interrupt
1447 * 0: Disable interrupt
1448 */
1449#define MR2_G_IEN                               (1<<6)
1450
1451
1452/**
1453 * @brief       No TCP Reset Packet send
1454 * @details This bit prevents sending reset packet.
1455 * 1: Block TCP reset packet send
1456 * 0: TCP Reset packet send
1457 */
1458#define MR2_NOTCPRST                    (1<<5)
1459
1460/**
1461 * @brief       Unreachable Packet Send Block bit
1462 * @details     This bit prevents sending Destination Port Unreachable Packet.
1463 * 1: Block Destination Port Unreachable Packet Send
1464 * 0: Destination Port Unreachable Packet Send
1465 */
1466#define MR2_UDPURB                              (1<<4)
1467
1468/**
1469 * @brief Wake On LAN
1470 * @details This bit enables WOL packet to be received.
1471 * 1: WOL packet can be received.
1472 * 0: WOL packet cannot be received.
1473 */
1474#define MR2_WOL                                 (1<<3)
1475
1476/**todo
1477 * @brief MACRAW No Size Check
1478 * @details
1479 */
1480#define MR2_MNOSCHK                             (1<<2)
1481
1482/**
1483 * @brief       UDP force ARP
1484 * @details This bit can enables to force ARP for each send command.
1485 * 1: UDP Force ARP Enable
1486 * 0: UDP Force ARP Disable.
1487 *
1488 */
1489#define MR2_UDPFARP                             (1<<1)
1490
1491/**todo
1492 * @brief       Skip SRC Hardware Address
1493 * @details     This bit can enables to receive without checking the hardware address of the peer.
1494 * 1:
1495 */
1496#define MR2_SSRCHA                              (1<<0)
1497
1498
1499
1500/* Common interrupt register 2 values */
1501
1502/**todo
1503 * @brief magic packet
1504 * @details
1505 */
1506#define IR2_MGC                         (1<<1)
1507
1508/**todo
1509 * @brief Magic packet interrupt mask bit
1510 * @details If this bit is set, each socket interrupt is enabled.
1511 */
1512#define IMR2_MGC                        (1<<1)
1513
1514/**todo
1515 * @brief
1516 * @details
1517 */
1518//#define IR2_MGD                               (1<<1) /* Reserved */
1519
1520
1521/* PHY status register 0 values */
1522
1523/**todo
1524 * @brief Ethernet CABLE OFF Signal
1525 * @details
1526 */
1527#define PHYSR_CABOFF                            (1<<7)
1528
1529/**todo
1530 * @brief
1531 * @details
1532 */
1533#define PHYSR_MD2                               (1<<5)
1534
1535/**todo
1536 * @brief
1537 * @details
1538 */
1539#define PHYSR_MD1                               (1<<4)
1540
1541/**todo
1542 * @brief
1543 * @details
1544 */
1545#define PHYSR_MD0                               (1<<3)
1546
1547/**todo
1548 * @brief
1549 * @details
1550 */
1551#define PHYSR_DUP                               (1<<2)
1552
1553/**todo
1554 * @brief
1555 * @details
1556 */
1557#define PHYSR_SPD                               (1<<1)
1558
1559/**todo
1560 * @brief LINKDONE register
1561 * @details If 1 Linked successfully, if 0 no link
1562 */
1563#define PHYSR_LNK                               (1<<0)
1564
1565
1566/* PHY status register 10 values */
1567
1568/**
1569 * @brieftodo
1570 * @details
1571 */
1572#define PHYSR1_RXPG                             (1<<2)
1573
1574/**
1575 * @brieftodo
1576 * @details
1577 */
1578#define PHYSR1_LPI                              (1<<1)
1579
1580/**
1581 * @brieftodo
1582 * @details
1583 */
1584#define PHYSR1_CLDN                             (1<<0)
1585
1586#define PHYCR_AUTONEGO_ENABLE   (0<<2)
1587#define PHYCR_AUTONEGO_DISABLE  (1<<2)
1588
1589#define PHYCR_SPD_10                    (1<<1)
1590#define PHYCR_SPD_100                   (0<<1)
1591
1592#define PHYCR_HALF_DUP                  (1<<0)
1593#define PHYCR_FULL_DUP                  (0<<0)
1594
1595#define PHYCR1_RST                              (0<<0)
1596
1597#define PHYCR1_PWDN_ENABLE              (1<<5)
1598#define PHYCR1_PWDN_DISABLE             (0<<5)
1599
1600
1601/* Socket n MODE register 2 values */
1602
1603/**
1604 * @brief Broadcast Blocking bit in MACRAW mode
1605 * @details In MACRAW mode, this bit is set to ????to block the broadcast packet.
1606 */
1607#define Sn_MR2_MBBLK                    (1<<6)
1608
1609/**
1610 * @brief Multicast Blocking bit in MACRAW mode
1611 * @details In MACRAW mode, this bit is set to ????to block the multicast packet.
1612 */
1613#define Sn_MR2_MMBLK                    (1<<5)
1614
1615/**
1616 * @brief IPv6 packet Blocking bit in MACRAW mode
1617 * @details In MACRAW mode, this bit is set to ????to block the IPv6 packet.
1618 */
1619#define Sn_MR2_IPV6BLK                  (1<<4)
1620
1621
1622/**
1623 * @brief Broadcast Blocking bit in UDP mode
1624 * @details In UDP mode, this bit is set to ????to block the broadcast packet.
1625 */
1626#define Sn_MR2_UBBLK                    (1<<1)
1627
1628
1629/**
1630 * @brief TCP Force PSH bit
1631 * @details When the SOCKET transmits data in TCP mode, PSH Flag is set to all packets.
1632 */
1633#define Sn_MR2_FPSH                     Sn_MR2_UBBLK
1634
1635/**
1636 * @brief Unicast Blocking bit in UDP mode
1637 * @details In UDP mode, this bit is set to ????to block the Unicast packet.
1638 */
1639#define Sn_MR2_UUBLK                    (1<<0)
1640
1641/*----------------------------For PHY Control-------------------------------*/
1642
1643/********************/
1644/* Register Address */
1645/********************/
1646
1647//Basic mode control register, basic register
1648#define PHYMDIO_BMCR                            0x00
1649
1650//Basic mode status register, basic register
1651#define PHYMDIO_BMSR                            0x01
1652
1653//--------------------------------------Not used-------------------------------------------//
1654////PHY identifier register 1, extended register
1655//#define PHY_IDR1                              0x02    //not used
1656//
1657////PHY identifier register 2, extended register
1658//#define PHY_IDR2                              0x03    //not used
1659//
1660////Auto-negotiation advertisement register, extended register
1661//#define PHY_ANAR                              0x04    //not used
1662//
1663////Auto-negotiation link partner ability register, extended register
1664//#define PHY_ANLPAR                            0x05    //not used
1665//
1666////Auto-negotiation expansion register, extended register
1667//#define PHY_ANER                              0x06    //not used
1668//
1669////Auto-negotiation next page transmit
1670//#define PHY_ANNP                              0x07    //not used
1671//
1672////Auto-negotiation link partner of the next page receive
1673//#define PHY_ANLPNP                            0x08    //not used
1674//
1675////MMD access control register
1676//#define PHY_REGCR                             0x09    //not used
1677//
1678////MMD access address data register
1679//#define PHY_ADDAR                             0x0e    //not used
1680//--------------------------------------Not used-------------------------------------------//
1681
1682/********************/
1683/* Bit definitions  */
1684/********************/
1685
1686//For BMCR register
1687#define BMCR_RESET                              (1<<15)
1688#define BMCR_MLOOPBACK                  (1<<14)
1689#define BMCR_SPEED                              (1<<13)
1690#define BMCR_AUTONEGO                   (1<<12)
1691#define BMCR_PWDN                               (1<<11)
1692#define BMCR_ISOLATE                    (1<<10)
1693#define BMCR_RSTNEGO                    (1<<9)
1694#define BMCR_DUP                                (1<<8)
1695#define BMCR_COLTEST                    (1<<7)
1696
1697//For BMSR register
1698#define BMSR_AUTONEGO_COMPL             (1<<5)
1699#define BMSR_REMOTE_FAULT               (1<<4)
1700#define BMSR_LINK_STATUS                (1<<2)
1701#define BMSR_JAB_DETECT                 (1<<1)
1702#define EXTENDED_CAPA                   (1<<0)
1703
1704//--------------------------------------Not used-------------------------------------------//
1705////For ANAR register
1706//#define ANAR_NP                                       (1<<15)
1707//#define ANAR_ACK                              (1<<14)
1708//#define ANAR_RF                                       (1<<13)
1709//#define ANAR_ASM                              (3<<10)
1710//#define ANAR_T4                                       (1<<9)
1711//#define ANAR_TX_FD                            (1<<8)
1712//#define ANAR_TX_HD                            (1<<7)
1713//#define ANAR_10_FD                            (1<<6)
1714//#define ANAR_10_HD                            (1<<5)
1715//#define ANAR_SELECTOR                 (0x1F<<0)
1716//
1717////For ANAR register
1718//#define ANLPAR_NP                             (1<<15)
1719//#define ANLPAR_ACK                            (1<<14)
1720//#define ANLPAR_RF                             (1<<13)
1721//#define ANLPAR_LP_DIR                 (1<<11)
1722//#define ANLPAR_PAUSE                  (1<<10)
1723//#define ANLPAR_T4                             (1<<9)
1724//#define ANLPAR_TX_FD                  (1<<8)
1725//#define ANLPAR_TX_HD                  (1<<7)
1726//#define ANLPAR_10_FD                  (1<<6)
1727//#define ANLPAR_10_HD                  (1<<5)
1728//#define ANLPAR_SELECTOR                       (0x1F<<0)
1729
1730/**/
1731/* MDIO register*/
1732//PCS_CTL_1                     |               PCS control 1 register
1733//PCS_STS_1                     |               PCS status 1 register
1734//EEE_ABILITY           |               EEE capability register
1735//WAKE_ER_CNTR          |               EEE wake error counter
1736//EEE_ADVR                      |               EEE Advertisement register
1737//EEE_LPAR                      |               EEE link partner ability register
1738
1739//--------------------------------------Not used-------------------------------------------//
1740
1741/********************/
1742/*Functions for PHY */
1743/********************/
1744//todo move this definition to bit area
1745#define PHYACR_READ                     0x02
1746#define PHYACR_WRITE            0x01
1747
1748
1749
1750
1751/**
1752 * @brief Enter a critical section
1753 *
1754 * @details It is provided to protect your shared code which are executed without distribution. \n \n
1755 *
1756 * In non-OS environment, It can be just implemented by disabling whole interrupt.\n
1757 * In OS environment, You can replace it to critical section api supported by OS.
1758 *
1759 * \sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
1760 * \sa WIZCHIP_CRITICAL_EXIT()
1761 */
1762#define WIZCHIP_CRITICAL_ENTER()    WIZCHIP.CRIS._enter()
1763
1764#ifdef _exit
1765#undef _exit
1766#endif
1767
1768/**
1769 * @brief Exit a critical section
1770 *
1771 * @details It is provided to protect your shared code which are executed without distribution. \n\n
1772 *
1773 * In non-OS environment, It can be just implemented by disabling whole interrupt. \n
1774 * In OS environment, You can replace it to critical section api supported by OS.
1775 *
1776 * @sa WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
1777 * @sa WIZCHIP_CRITICAL_ENTER()
1778 */
1779#define WIZCHIP_CRITICAL_EXIT()     WIZCHIP.CRIS._exit()
1780
1781
1782
1783////////////////////////
1784// Basic I/O Function //
1785////////////////////////
1786//
1787//M20150601 :  uint16_t AddrSel --> uint32_t AddrSel
1788//
1789/**
1790 * @ingroup Basic_IO_function_W5100S
1791 * @brief It reads 1 byte value from a register.
1792 * @param AddrSel Register address
1793 * @return The value of register
1794 */
1795uint8_t  WIZCHIP_READ (uint32_t AddrSel);
1796
1797/**
1798 * @ingroup Basic_IO_function_W5100S
1799 * @brief It writes 1 byte value to a register.
1800 * @param AddrSel Register address
1801 * @param wb Write data
1802 * @return void
1803 */
1804void     WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1805
1806/**
1807 * @ingroup Basic_IO_function_W5100S
1808 * @brief It reads sequence data from registers.
1809 * @param AddrSel Register address
1810 * @param pBuf Pointer buffer to read data
1811 * @param len Data length
1812 */
1813void     WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1814
1815/**
1816 * @ingroup Basic_IO_function_W5100S
1817 * @brief It writes sequence data to registers.
1818 * @param AddrSel Register address
1819 * @param pBuf Pointer buffer to write data
1820 * @param len Data length
1821 */
1822void     WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1823
1824
1825/////////////////////////////////
1826// Common Register IO function //
1827/////////////////////////////////
1828
1829/**
1830 * @ingroup Common_register_access_function_W5100S
1831 * @brief Set Mode Register
1832 * @param (uint8_t)mr The value to be set.
1833 * @sa getMR()
1834 */
1835#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1836   #define setMR(mr)    WIZCHIP_WRITE(MR,mr)
1837#else
1838   #define setMR(mr)    (*((uint8_t*)MR) = mr)
1839#endif
1840
1841/**
1842 * @ingroup Common_register_access_function_W5100S
1843 * @brief Get @ref MR.
1844 * @return uint8_t. The value of Mode register.
1845 * @sa setMR()
1846 */
1847#if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1848   #define getMR()              WIZCHIP_READ(MR)
1849#else
1850   #define getMR()      (*(uint8_t*)MR)
1851#endif
1852
1853/**
1854 * @ingroup Common_register_access_function_W5100S
1855 * @brief Set @ref GAR.
1856 * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
1857 * @sa getGAR()
1858 */
1859#define setGAR(gar) \
1860                WIZCHIP_WRITE_BUF(GAR,gar,4)
1861
1862/**
1863 * @ingroup Common_register_access_function_W5100S
1864 * @brief Get @ref GAR.
1865 * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
1866 * @sa setGAR()
1867 */
1868#define getGAR(gar) \
1869                WIZCHIP_READ_BUF(GAR,gar,4)
1870
1871/**
1872 * @ingroup Common_register_access_function_W5100S
1873 * @brief Set @ref SUBR.
1874 * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
1875 * @note If subr is null pointer, set the backup subnet to SUBR. \n
1876 *       If subr is 0.0.0.0, back up SUBR and clear it. \n
1877 *       Otherwize, set subr to SUBR
1878 * @sa getSUBR()
1879 */
1880#define setSUBR(subr) \
1881      WIZCHIP_WRITE_BUF(SUBR,subr,4)
1882
1883/**
1884 * @ingroup Common_register_access_function_W5100S
1885 * @brief Get @ref SUBR.
1886 * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
1887 * @sa setSUBR()
1888 */
1889#define getSUBR(subr) \
1890                WIZCHIP_READ_BUF(SUBR, subr, 4)
1891
1892/**
1893 * @ingroup Common_register_access_function_W5100S
1894 * @brief Set @ref SHAR.
1895 * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
1896 * @sa getSHAR()
1897 */
1898#define setSHAR(shar) \
1899                WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1900
1901/**
1902 * @ingroup Common_register_access_function_W5100S
1903 * @brief Get @ref SHAR.
1904 * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
1905 * @sa setSHAR()
1906 */
1907#define getSHAR(shar) \
1908                WIZCHIP_READ_BUF(SHAR, shar, 6)
1909
1910/**
1911 * @ingroup Common_register_access_function_W5100S
1912 * @brief Set @ref SIPR.
1913 * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
1914 * @sa getSIPR()
1915*/
1916#define setSIPR(sipr) \
1917                WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1918
1919/**
1920 * @ingroup Common_register_access_function_W5100S
1921 * @brief Get @ref SIPR.
1922 * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
1923 * @sa setSIPR()
1924 */
1925#define getSIPR(sipr) \
1926                WIZCHIP_READ_BUF(SIPR, sipr, 4)
1927
1928/**
1929 * @ingroup Common_register_access_function_W5100S
1930 * @brief Set \ref IR register
1931 * @param (uint8_t)ir Value to set \ref IR register.
1932 * @sa getIR()
1933 */
1934#define setIR(ir) \
1935                WIZCHIP_WRITE(IR, (ir & 0xE0)) //peter 2016.11.07 unreachable interrupt bit added
1936                //WIZCHIP_WRITE(IR, (ir & 0xA0))
1937/**
1938 * @ingroup Common_register_access_function_W5100S
1939 * @brief Get \ref IR register
1940 * @return uint8_t. Value of \ref IR register.
1941 * @sa setIR()
1942 */
1943#define getIR() \
1944                WIZCHIP_READ(IR)
1945
1946/**
1947 * @ingroup Common_register_access_function_W5100S
1948 * @brief Set \ref _IMR_ register
1949 * @param (uint8_t)imr Value to set @ref _IMR_ register.
1950 * @sa getIMR()
1951 */
1952#define setIMR(imr) \
1953                WIZCHIP_WRITE(_IMR_, imr)
1954
1955/**
1956 * @ingroup Common_register_access_function_W5100S
1957 * @brief Get \ref _IMR_ register
1958 * @return uint8_t. Value of @ref _IMR_ register.
1959 * @sa setIMR()
1960 */
1961#define getIMR() \
1962                WIZCHIP_READ(_IMR_)
1963
1964/**
1965 * @ingroup Common_register_access_function_W5100S
1966 * @brief Set \ref _RTR_ register
1967 * @param (uint16_t)rtr Value to set @ref _RTR_ register.
1968 * @sa getRTR()
1969 */
1970#define setRTR(rtr)   {\
1971                WIZCHIP_WRITE(_RTR_,   (uint8_t)(rtr >> 8)); \
1972                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1973        }
1974
1975/**
1976 * @ingroup Common_register_access_function_W5100S
1977 * @brief Get \ref _RTR_ register
1978 * @return uint16_t. Value of @ref _RTR_ register.
1979 * @sa setRTR()
1980 */
1981#define getRTR() \
1982                (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1983
1984/**
1985 * @ingroup Common_register_access_function_W5100S
1986 * @brief Set \ref _RCR_ register
1987 * @param (uint8_t)rcr Value to set @ref _RCR_ register.
1988 * @sa getRCR()
1989 */
1990#define setRCR(rcr) \
1991                WIZCHIP_WRITE(_RCR_, rcr)
1992
1993/**
1994 * @ingroup Common_register_access_function_W5100S
1995 * @brief Get \ref _RCR_ register
1996 * @return uint8_t. Value of @ref _RCR_ register.
1997 * @sa setRCR()
1998 */
1999#define getRCR() \
2000                WIZCHIP_READ(_RCR_)
2001
2002/**
2003 * @ingroup Common_register_access_function_W5100S
2004 * @brief Get \ref RMSR register
2005 * @sa getRMSR()
2006 */
2007#define setRMSR(rmsr)   \
2008      WIZCHIP_WRITE(RMSR,rmsr) // Receicve Memory Size
2009
2010/**
2011 * @ingroup Common_register_access_function_W5100S
2012 * @brief Get \ref RMSR register
2013 * @return uint8_t. Value of @ref RMSR register.
2014 * @sa setRMSR()
2015 */
2016 #define getRMSR()   \
2017      WIZCHIP_READ(RMSR) // Receicve Memory Size
2018
2019/**
2020 * @ingroup Common_register_access_function_W5100S
2021 * @brief Get \ref TMSR register
2022 * @sa getTMSR()
2023 */
2024#define setTMSR(tmsr)   \
2025      WIZCHIP_WRITE(TMSR,tmsr) // Receicve Memory Size
2026
2027/**
2028 * @ingroup Common_register_access_function_W5100S
2029 * @brief Get \ref TMSR register
2030 * @return uint8_t. Value of @ref TMSR register.
2031 * @sa setTMSR()
2032 */
2033#define getTMSR()       \
2034        WIZCHIP_READ(TMSR)
2035
2036
2037/**
2038 * @ingroup Common_register_access_function_W5100S
2039 * @brief Get \ref PATR register
2040 * @return uint16_t. Value to set \ref PATR register
2041 */
2042#define getPATR() \
2043                (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
2044
2045/**
2046 * @ingroup Common_register_access_function_W5100S
2047 * @brief Get \ref PPPALGO register
2048 * @return uint8_t. Value to set \ref PPPALGO register
2049 */
2050#define getPPPALGO() \
2051                WIZCHIP_READ(PPPALGO)
2052
2053
2054/**
2055 * @ingroup Common_register_access_function_W5100S
2056 * @brief Set \ref PTIMER register
2057 * @param (uint8_t)ptimer Value to set \ref PTIMER register.
2058 * @sa getPTIMER()
2059 */
2060#define setPTIMER(ptimer) \
2061                WIZCHIP_WRITE(PTIMER, ptimer)
2062
2063/**
2064 * @ingroup Common_register_access_function_W5100S
2065 * @brief Get \ref PTIMER register
2066 * @return uint8_t. Value of @ref PTIMER register.
2067 * @sa setPTIMER()
2068 */
2069#define getPTIMER() \
2070                WIZCHIP_READ(PTIMER)
2071
2072/**
2073 * @ingroup Common_register_access_function_W5100S
2074 * @brief Set \ref PMAGIC register
2075 * @param (uint8_t)pmagic Value to set @ref PMAGIC register.
2076 * @sa getPMAGIC()
2077 */
2078#define setPMAGIC(pmagic) \
2079                WIZCHIP_WRITE(PMAGIC, pmagic)
2080
2081/**
2082 * @ingroup Common_register_access_function_W5100S
2083 * @brief Get \ref PMAGIC register
2084 * @return uint8_t. Value of @ref PMAGIC register.
2085 * @sa setPMAGIC()
2086 */
2087#define getPMAGIC() \
2088                WIZCHIP_READ(PMAGIC)
2089
2090
2091//todo Functions for W5100S
2092
2093/*----------------------------------------------------------------------*/
2094/*                                                              W5100S only                                                             */
2095/*----------------------------------------------------------------------*/
2096
2097/**
2098 * @ingroup Common_register_access_function_W5100S
2099 * @brief Set \ref IR2 register
2100 * @param (uint8_t)ir2 Value to set @ref IR2 register.
2101 * @sa getIR2()
2102 */
2103#define setIR2(ir2) \
2104                WIZCHIP_WRITE(IR2, ir2)
2105
2106/**
2107 * @ingroup Common_register_access_function_W5100S
2108 * @brief Get \ref IR2 register
2109 * @return uint8_t. Value of @ref IR2 register.
2110 * @sa setIR2()
2111 */
2112#define getIR2() \
2113                WIZCHIP_READ(IR2)
2114
2115/**
2116 * @ingroup Common_register_access_function_W5100S
2117 * @brief Set \ref IMR2 register
2118 * @param (uint8_t)imr2 Value to set @ref IMR2 register.
2119 * @sa setIMR2()
2120 */
2121#define setIMR2(imr2) \
2122                WIZCHIP_WRITE(IMR2,imr2)
2123
2124/**
2125 * @ingroup Common_register_access_function_W5100S
2126 * @brief Get \ref IMR2 register
2127 * @return uint8_t. Value of @ref IMR2 register.
2128 * @sa getIMR2()
2129 */
2130#define getIMR2() \
2131                WIZCHIP_READ(IMR2)
2132
2133/**
2134 * @ingroup Common_register_access_function_W5100S
2135 * @brief Set \ref UIPR(Unreachable IP Address Register) registers
2136 * @param (uint8_t*)uipr Value to set @ref UIPR registers.
2137 * @sa setUIPR()
2138 */
2139#define setUIPR(uipr) \
2140                WIZCHIP_WRITE_BUF(UIPR,uipr,4)
2141
2142/**
2143 * @ingroup Common_register_access_function_W5100S
2144 * @brief Get \ref UIPR(Unreachable IP Address Register) registers
2145 * @param (uint8_t*)uipr Value to get @ref UIPR registers
2146 * @sa setUIPR()
2147 */
2148#define getUIPR(uipr) \
2149                WIZCHIP_READ_BUF(UIPR,uipr,4)
2150
2151/**
2152 * @ingroup Common_register_access_function_W5100S
2153 * @brief Set \ref UPORTR(Unreachable Port Address Register) register
2154 * @param (uint16_t)uportr Value to set @ref UPORTR register.
2155 * @sa getUPORTR()
2156 */
2157#define setUPORTR(uportr) {\
2158                WIZCHIP_WRITE(UPORTR, (uint8_t)(uportr >> 8)); \
2159                WIZCHIP_WRITE(UPORTR+1, (uint8_t) uportr); \
2160        }
2161
2162/**
2163 * @ingroup Common_register_access_function_W5100S
2164 * @brief Get \ref UPORTR(Unreachable Port Address Register) register
2165 * @return uint16_t. Value of @ref UPORTR register.
2166 * @sa setUPORTR()
2167 */
2168#define getUPORTR() \
2169                (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(UPORTR+1))
2170
2171/**
2172 * @ingroup Common_register_access_function_W5100S
2173 * @brief Set \ref MR2 register
2174 * @param (uint8_t)mr2 Value to set @ref MR2 registers.
2175 * @sa getMR2()
2176 */
2177#define setMR2(mr2) \
2178                WIZCHIP_WRITE(MR2,mr2)
2179
2180/**
2181 * @ingroup Common_register_access_function_W5100S
2182 * @brief Get \ref MR2 register
2183 * @return uint8_t. Value of @ref MR2 register.
2184 * @sa setMR2()
2185 */
2186#define getMR2() \
2187                WIZCHIP_READ(MR2)
2188
2189/**
2190 * @ingroup Common_register_access_function_W5100S
2191 * @brief Set \ref PHAR registers
2192 * @param (uint8_t*)phar Value to set @ref PHAR registers.
2193 * @sa getPHAR()
2194 */
2195#define setPHAR(phar) \
2196                WIZCHIP_WRITE_BUF(PHAR,phar,6)
2197
2198/**
2199 * @ingroup Common_register_access_function_W5100S
2200 * @brief Get \ref PHAR registers
2201 * @param (uint8_t*)phar Pointer variable to get @ref PHAR registers.
2202 * @sa setPHAR()
2203 */
2204#define getPHAR(phar) \
2205                WIZCHIP_READ_BUF(PHAR,phar,6)
2206
2207/**
2208 * @ingroup Common_register_access_function_W5100S
2209 * @brief Set \ref PSIDR register
2210 * @param (uint16_t)psidr Value to set @ref PSIDR register.
2211 * @sa getPSIDR()
2212 */
2213#define setPSIDR(psidr) {\
2214                WIZCHIP_WRITE(PSIDR, (uint8_t)(psidr >> 8)); \
2215                WIZCHIP_WRITE(PSIDR+1, (uint8_t) psidr); \
2216        }
2217
2218/**
2219 * @ingroup Common_register_access_function_W5100S
2220 * @brief Get \ref PSIDR register
2221 * @return uint16_t. Value of @ref PSIDR register.
2222 * @sa setPSIDR()
2223 */
2224#define getPSIDR() \
2225                (((uint16_t)WIZCHIP_READ(PSIDR) << 8) + WIZCHIP_READ(PSIDR+1))
2226
2227/**
2228 * @ingroup Common_register_access_function_W5100S
2229 * @brief Set \ref PMRUR register
2230 * @param (uint16_t)pmrur Value to set @ref PMRUR register.
2231 * @sa getPMRUR()
2232 */
2233#define setPMRUR(pmrur) {\
2234                WIZCHIP_WRITE(PMRUR, (uint8_t)(pmrur >> 8)); \
2235                WIZCHIP_WRITE(PMRUR+1, (uint8_t) pmrur); \
2236        }
2237
2238/**
2239 * @ingroup Common_register_access_function_W5100S
2240 * @brief Get \ref PMRUR register
2241 * @return uint16_t. Value of @ref PMRUR register.
2242 * @sa setPMRUR()
2243 */
2244#define getPMRUR() \
2245                (((uint16_t)WIZCHIP_READ(PMRUR) << 8) + WIZCHIP_READ(PMRUR+1))
2246
2247/**
2248 * @ingroup Common_register_access_function_W5100S
2249 * @brief Get \ref PHYSR register
2250 * @return uint8_t. Value of @ref PHYSR register.
2251 * @sa setPHYSR()
2252 */
2253#define getPHYSR()      \
2254                WIZCHIP_READ(PHYSR)
2255
2256/**
2257 * @ingroup Common_register_access_function_W5100S
2258 * @brief Get \ref PHYSR1 register
2259 * @return uint8_t. Value of @ref PHYSR1 register.
2260 * @sa setPHYSR1()
2261 */
2262#define getPHYSR1()     \
2263                WIZCHIP_READ(PHYSR1)
2264
2265/**
2266 * For internal uses
2267 * The address of the PHY is fixed as "0x0A".
2268 */
2269#define getPHYAR() \
2270                WIZCHIP_READ(PHYAR)
2271
2272/**
2273 * @ingroup Common_register_access_function_W5100S
2274 * @brief Get \ref PHYRAR register
2275 * @return uint8_t. Value of @ref PHYRAR register.
2276 * @sa setPHYRAR()
2277 */
2278#define getPHYRAR() \
2279                WIZCHIP_READ(PHYRAR)
2280
2281/**
2282 * @ingroup Common_register_access_function_W5100S
2283 * @brief Set \ref PHYRR register
2284 * @param (uint8_t)phyrar Value to set @ref PHYRR register.
2285 * @sa getPHYRR()
2286 */
2287#define setPHYRR(phyrar) \
2288                WIZCHIP_WRITE(PHYRAR, phyrar)
2289
2290/**
2291 * @ingroup Common_register_access_function_W5100S
2292 * @brief Get \ref PHYDIR register
2293 * @return uint16_t. Value of @ref PHYDIR register.
2294 * @sa setPHYRAR()
2295 */
2296//read the value of the phy data input register
2297#define getPHYDIR() \
2298                (((uint16_t)WIZCHIP_READ(PHYDIR+1) << 8) + WIZCHIP_READ(PHYDIR))
2299
2300/**
2301 * @ingroup Common_register_access_function_W5100S
2302 * @brief Set \ref PHYDIR register
2303 * @param (uint16_t)phydir Value to set @ref PHYDIR register.
2304 * @sa getPHYDIR()
2305 */
2306//write the value of the phy data input register
2307#define setPHYDIR(phydir) {\
2308                WIZCHIP_WRITE(PHYDIR+1, (uint8_t)(phydir >> 8)); \
2309                WIZCHIP_WRITE(PHYDIR, (uint8_t) phydir); \
2310        }
2311
2312/**
2313 * @ingroup Common_register_access_function_W5100S
2314 * @brief Get \ref PHYDOR register
2315 * @return uint16_t. Value of @ref PHYDOR register.
2316 * @sa setPHYDOR()
2317 */
2318//read the value of the phy data output register
2319#define getPHYDOR()     \
2320                (((uint16_t)WIZCHIP_READ(PHYDOR+1) << 8) + WIZCHIP_READ(PHYDOR))
2321
2322/**
2323 * @ingroup Common_register_access_function_W5100S
2324 * @brief Set \ref PHYDOR register
2325 * @param (uint16_t)phydor Value to set @ref PHYDOR register.
2326 * @sa getPHYDOR()
2327 */
2328//write the value of the phy data output register
2329#define setPHYDOR(phydor) {\
2330                WIZCHIP_WRITE(PHYDOR, (uint8_t)(phydor >> 8)); \
2331                WIZCHIP_WRITE(PHYDOR+1, (uint8_t) phydor); \
2332        }
2333
2334/**
2335 * @ingroup Common_register_access_function_W5100S
2336 * @brief Get \ref PHYACR register
2337 * @return uint8_t. Value of @ref PHYACR register.
2338 * @sa setPHYACR()
2339 */
2340//read the value of the phy action register ***This register will be cleared automatically***
2341#define getPHYACR() \
2342                WIZCHIP_READ(PHYACR)
2343
2344/**
2345 * @ingroup Common_register_access_function_W5100S
2346 * @brief Set \ref PHYACR register
2347 * @param (uint8_t)phyacr Value to set @ref PHYACR register.
2348 * @sa getPHYACR()
2349 */
2350//write the value of the phy action register
2351#define setPHYACR(phyacr)       \
2352                WIZCHIP_WRITE(PHYACR,phyacr)
2353
2354/**
2355 * @ingroup Common_register_access_function_W5100S
2356 * @brief Set \ref PHYDIVR register
2357 * @param (uint8_t)phydivr Value to set @ref PHYDIVR register.
2358 * @sa getPHYDIVR()
2359 */
2360#define setPHYDIVR(phydivr)     \
2361                WIZCHIP_WRITE(PHYDIVR, phydivr)
2362
2363/**
2364 * @ingroup Common_register_access_function_W5100S
2365 * @brief Get \ref PHYDIVR register
2366 * @return uint8_t. Value of @ref PHYDIVR register.
2367 * @sa setPHYDIVR()
2368 */
2369#define getPHYDIVR()    \
2370                WIZCHIP_READ(PHYDIVR)
2371
2372/**
2373 * @ingroup Common_register_access_function_W5100S
2374 * @brief Set \ref PHYCR0 register
2375 * @param (uint8_t)phych0 Value to set @ref PHYCR0 register.
2376 * @sa getPHYCR0()
2377 */
2378#define setPHYCR0(phych0)               \
2379                WIZCHIP_WRITE(PHYCR0,phych0)
2380
2381/**
2382 * @ingroup Common_register_access_function_W5100S
2383 * @brief Get \ref PHYCR0 register
2384 * @return uint8_t. Value of @ref PHYCR0 register.
2385 * @sa setPHYCR0()
2386 */
2387#define getPHYCR0()     \
2388                WIZCHIP_READ(PHYCR0)
2389
2390/**
2391 * @ingroup Common_register_access_function_W5100S
2392 * @brief Set \ref PHYCR1 register
2393 * @param (uint8_t)phycr1 Value to set @ref PHYCR1 register.
2394 * @sa getPHYCR1()
2395 */
2396#define setPHYCR1(phycr1)       \
2397                WIZCHIP_WRITE(PHYCR1,phycr1)
2398
2399/**
2400 * @ingroup Common_register_access_function_W5100S
2401 * @brief Get \ref PHYCR1 register
2402 * @return uint8_t. Value of @ref PHYCR1 register.
2403 * @sa setPHYCR1()
2404 */
2405#define getPHYCR1() \
2406                WIZCHIP_READ(PHYCR1)
2407
2408/**
2409 * @ingroup Common_register_access_function_W5100S
2410 * @brief Set \ref SLCR register
2411 * @param (uint8_t)rqcr Value to set @ref SLCR register.
2412 * @sa getSLCR()
2413 */
2414#define setSLCR(rqcr)   \
2415                WIZCHIP_WRITE(SLCR, rqcr)
2416
2417/**
2418 * @ingroup Common_register_access_function_W5100S
2419 * @brief Get \ref SLCR register
2420 * @return uint8_t. Value of @ref SLCR register.
2421 * @sa setSLCR()
2422 */
2423#define getSLCR()       \
2424                WIZCHIP_READ(SLCR)
2425
2426/**
2427 * @ingroup Common_register_access_function_W5100S
2428 * @brief Set \ref SLRTR register
2429 * @param (uint16_t)slrtr Value to set @ref SLRTR register.
2430 * @sa getSLRTR()
2431 */
2432#define setSLRTR(slrtr) \
2433                WIZCHIP_WRITE(SLRTR, (uint8_t)(slrtr >> 8)); \
2434                WIZCHIP_WRITE(SLRTR+1, (uint8_t) slrtr); \
2435
2436/**
2437 * @ingroup Common_register_access_function_W5100S
2438 * @brief Get \ref SLRTR register
2439 * @return uint16_t. Value of @ref SLRTR register.
2440 * @sa setSLRTR()
2441 */
2442#define getSLRTR()      \
2443                (((uint16_t)WIZCHIP_READ(SLRTR) << 8) + WIZCHIP_READ(SLRTR+1))
2444
2445/**
2446 * @ingroup Common_register_access_function_W5100S
2447 * @brief Set \ref SLRCR register
2448 * @param (uint8_t)slrcr Value to set @ref SLRCR register.
2449 * @sa getSLRCR()
2450 */
2451#define setSLRCR(slrcr) \
2452                WIZCHIP_WRITE(SLRCR,slrcr)
2453
2454/**
2455 * @ingroup Common_register_access_function_W5100S
2456 * @brief Get \ref SLRCR register
2457 * @return uint8_t. Value of @ref SLRCR register.
2458 * @sa setSLRCR()
2459 */
2460#define getSLRCR()      \
2461                WIZCHIP_READ(SLRCR)
2462
2463/**
2464 * @ingroup Common_register_access_function_W5100S
2465 * @brief Set \ref SLPIPR registers
2466 * @param (uint8_t*)slpipr Values to set @ref SLPIPR registers.
2467 * @sa getSLPIPR()
2468 */
2469#define setSLPIPR(slpipr)       \
2470                WIZCHIP_WRITE_BUF(SLPIPR,slpipr,4)
2471
2472/**
2473 * @ingroup Common_register_access_function_W5100S
2474 * @brief Get \ref SLPIPR registers
2475 * @param (uint8_t*)slpipr Values to get @ref SLPIPR registers.
2476 * @sa getSLPIPR()
2477 */
2478#define getSLPIPR(slpipr)       \
2479                WIZCHIP_READ_BUF(SLPIPR,slpipr,4)
2480
2481/**
2482 * @ingroup Common_register_access_function_W5100S
2483 * @brief Get \ref SLPHAR registers
2484 * @param (uint8_t*)slphar Values to set @ref SLPHAR registers.
2485 * @sa getSLPHAR()
2486 */
2487#define setSLPHAR(slphar) \
2488                WIZCHIP_WRITE_BUF(SLPHAR,slphar,6)
2489
2490/**
2491 * @ingroup Common_register_access_function_W5100S
2492 * @brief Get \ref SLPHAR registers
2493 * @param (uint8_t*)slphar Values to get @ref SLPHAR registers.
2494 * @sa getSLPHAR()
2495 */
2496#define getSLPHAR(slphar) \
2497                WIZCHIP_READ_BUF(SLPHAR,slphar,6)
2498
2499/**
2500 * @ingroup Common_register_access_function_W5100S
2501 * @brief Set \ref PINGSEQR register
2502 * @param (uint16_t)pingseqr Value to set @ref PINGSEQR register.
2503 * @sa getPINGSEQR()
2504 */
2505#define setPINGSEQR(pingseqr) {\
2506                WIZCHIP_WRITE(PINGSEQR, (uint8_t)(pingseqr >> 8)); \
2507                WIZCHIP_WRITE(PINGSEQR+1, (uint8_t) pingseqr); \
2508        }
2509
2510/**
2511 * @ingroup Common_register_access_function_W5100S
2512 * @brief Get \ref PINGSEQR register
2513 * @return uint16_t. Value of @ref PINGSEQR register.
2514 * @sa setPINGSEQR()
2515 */
2516#define getPINGSEQR() \
2517                (((uint16_t)WIZCHIP_READ(PINGSEQR) << 8) + WIZCHIP_READ(PINGSEQR+1))
2518
2519/**
2520 * @ingroup Common_register_access_function_W5100S
2521 * @brief Set \ref PINGIDR register
2522 * @param (uint16_t)pingidr Value to set @ref PINGIDR register.
2523 * @sa getPINGIDR()
2524 */
2525#define setPINGIDR(pingidr) {\
2526                WIZCHIP_WRITE(PINGIDR, (uint8_t)(pingidr >> 8)); \
2527                WIZCHIP_WRITE(PINGIDR+1, (uint8_t) pingidr); \
2528        }
2529
2530/**
2531 * @ingroup Common_register_access_function_W5100S
2532 * @brief Get \ref PINGIDR register
2533 * @return uint16_t. Value of @ref PINGIDR register.
2534 * @sa setPINGIDR()
2535 */
2536#define getPINGIDR()    \
2537                (((uint16_t)WIZCHIP_READ(PINGIDR) << 8) + WIZCHIP_READ(PINGIDR+1))
2538
2539/**
2540 * @ingroup Common_register_access_function_W5100S
2541 * @brief Set \ref SLIMR register
2542 * @param (uint8_t)slimr Value to set @ref SLIMR register.
2543 * @sa getSLIMR()
2544 */
2545#define setSLIMR(slimr) \
2546                WIZCHIP_WRITE(SLIMR, slimr)
2547
2548/**
2549 * @ingroup Common_register_access_function_W5100S
2550 * @brief Get \ref SLIMR register
2551 * @return uint8_t. Value of @ref SLIMR register.
2552 * @sa setSLIMR()
2553 */
2554#define getSLIMR()      \
2555                WIZCHIP_READ(SLIMR)
2556
2557/**
2558 * @ingroup Common_register_access_function_W5100S
2559 * @brief Set \ref SLIR register
2560 * @param (uint8_t)slir Value to set @ref SLIR register.
2561 * @sa getSLIMR()
2562 */
2563#define setSLIR(slir)   \
2564                WIZCHIP_WRITE(SLIR, slir)
2565
2566/**
2567 * @ingroup Common_register_access_function_W5100S
2568 * @brief Get \ref SLIMR register
2569 * @return uint8_t. Value of @ref SLIMR register.
2570 * @sa setSLIMR()
2571 */
2572#define getSLIR()       \
2573                WIZCHIP_READ(SLIR)
2574
2575/*Hidden functions for W5100S*/
2576#define setDBGOUT(dbgout)       {\
2577                WIZCHIP_WRITE(DBGOUT,(uint8_t)(dbgout >> 16));  \
2578                WIZCHIP_WRITE(DBGOUT,(uint8_t)(dbgout >> 8));   \
2579                WIZCHIP_WRITE(DBGOUT,(uint8_t)(dbgout));                \
2580        }
2581
2582/**
2583 * @ingroup Common_register_access_function_W5100S
2584 * @brief Set \ref NICMAXCOLR register
2585 * @param (uint8_t)nicmaxcolr Value to set @ref NICMAXCOLR register.
2586 * @sa getNICMAXCOLR()
2587 */
2588#define setNICMAXCOLR(nicmaxcolr)       \
2589                WIZCHIP_WRITE(NICMAXCOLR,nicmaxcolr)
2590
2591/**
2592 * @ingroup Common_register_access_function_W5100S
2593 * @brief Get \ref NICMAXCOLR register
2594 * @return uint8_t. Value of @ref NICMAXCOLR register.
2595 * @sa setNICMAXCOLR()
2596 */
2597#define getNICMAXCOLR() \
2598                WIZCHIP_READ(NICMAXCOLR)
2599
2600/*Clock lock/unlock*/
2601
2602/**
2603 * @ingroup Common_register_access_function_W5100S
2604 * @brief LOCK Chip Information
2605 * @sa CHIPULLOCK()
2606 */
2607#define CHIPLOCK()      \
2608                WIZCHIP_WRITE(CHIPLCKR,0xff)
2609
2610/**
2611 * @ingroup Common_register_access_function_W5100S
2612 * @brief Unlock Chip Information
2613 * @sa CHIPLOCK()
2614 */
2615#define CHIPUNLOCK()    \
2616                WIZCHIP_WRITE(CHIPLCKR,0xCE)
2617
2618
2619/**
2620 * @ingroup Common_register_access_function_W5100S
2621 * @brief LOCK Chip Information
2622 * @sa CHIPULLOCK()
2623 */
2624/*Network information lock/unlock*/
2625#define NETLOCK()       \
2626                WIZCHIP_WRITE(NETLCKR,0x3A)
2627
2628/**
2629 * @ingroup Common_register_access_function_W5100S
2630 * @brief Unlock Chip Information
2631 * @sa CHIPLOCK()
2632 */
2633#define NETUNLOCK()     \
2634                WIZCHIP_WRITE(NETLCKR,0xC5)
2635
2636/**
2637 * @ingroup Common_register_access_function_W5100S
2638 * @brief Lock PHYCR0,CR1 Information
2639 * @sa CHIPULLOCK()
2640 */
2641/*PHY CR0,CR1 lock/unlock*/
2642#define PHYLOCK()       \
2643                WIZCHIP_WRITE(PHYLCKR,0xff)
2644
2645/**
2646 * @ingroup Common_register_access_function_W5100S
2647 * @brief Lock PHYCR0,CR1 Information
2648 * @sa CHIPULLOCK()
2649 */
2650#define PHYUNLOCK()     \
2651                WIZCHIP_WRITE(PHYLCKR,0x53)
2652
2653/**
2654 * @ingroup Version register_access_function_W5100SS
2655 * @brief Get version information.
2656 * @return uint16_t. It must be "0x51"
2657 */
2658#define getVER() \
2659                (WIZCHIP_READ(VERR))
2660
2661/**
2662 * @ingroup Common_register_access_function_W5100S
2663 * @brief Get \ref TCNTR register
2664 * @return uint16_t. Value of @ref TCNTR register.
2665 * @sa setNTCNTR()
2666 */
2667/*Get 100us internal counter*/
2668#define getTCNTR()      \
2669                (((uint16_t)WIZCHIP_READ(TCNTR) << 8) + WIZCHIP_READ(TCNTR+1))
2670
2671/**
2672 * @ingroup Common_register_access_function_W5100S
2673 * @brief Set \ref TCNTR register
2674 * @param (uint8_t)
2675  Value to set @ref TCNTR register.
2676 * @sa getTCNTCLKR()
2677 */
2678/*Reset 100us internal counter(TCNTR)*/
2679#define setTCNTCLKR(var)        \
2680                WIZCHIP_WRITE(TCNTCLKR, var)
2681
2682/*w5100s only end*/
2683
2684
2685
2686
2687
2688///////////////////////////////////
2689// Socket N register I/O function //
2690///////////////////////////////////
2691/**
2692 * @ingroup Socket_register_access_function_W5100S
2693 * @brief Set @ref Sn_MR register
2694 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
2695 * @param mr Value to set @ref Sn_MR
2696 * @sa getSn_MR()
2697 */
2698#define setSn_MR(sn, mr) \
2699                WIZCHIP_WRITE(Sn_MR(sn),mr)
2700
2701/**
2702 * @ingroup Socket_register_access_function_W5100S
2703 * @brief Get @ref Sn_MR register
2704 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b> expect <b>bit 4</b>.
2705 * @return Value of @ref Sn_MR.
2706 * @sa setSn_MR()
2707 */
2708#define getSn_MR(sn) \
2709        WIZCHIP_READ(Sn_MR(sn))
2710
2711/**
2712 * @ingroup Socket_register_access_function_W5100S
2713 * @brief Set @ref Sn_CR register
2714 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2715 * @param (uint8_t)cr Value to set @ref Sn_CR
2716 * @sa getSn_CR()
2717 */
2718#define setSn_CR(sn, cr) \
2719                WIZCHIP_WRITE(Sn_CR(sn), cr)
2720
2721/**
2722 * @ingroup Socket_register_access_function_W5100S
2723 * @brief Get @ref Sn_CR register
2724 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2725 * @return uint8_t. Value of @ref Sn_CR.
2726 * @sa setSn_CR()
2727 */
2728#define getSn_CR(sn) \
2729                WIZCHIP_READ(Sn_CR(sn))
2730
2731/**
2732 * @ingroup Socket_register_access_function_W5100S
2733 * @brief Set @ref Sn_IR register
2734 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2735 * @param (uint8_t)ir Value to set @ref Sn_IR
2736 * @sa getSn_IR()
2737 */
2738#define setSn_IR(sn, ir) \
2739                WIZCHIP_WRITE(Sn_IR(sn), ir)
2740
2741/**
2742 * @ingroup Socket_register_access_function_W5100S
2743 * @brief Get @ref Sn_IR register
2744 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2745 * @return uint8_t. Value of @ref Sn_IR.
2746 * @sa setSn_IR()
2747 */
2748#define getSn_IR(sn) \
2749                WIZCHIP_READ(Sn_IR(sn))
2750
2751/**
2752 * @ingroup Socket_register_access_function_W5100S
2753 * @brief Get @ref Sn_SR register
2754 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2755 * @return uint8_t. Value of @ref Sn_SR.
2756 */
2757#define getSn_SR(sn) \
2758                WIZCHIP_READ(Sn_SR(sn))
2759
2760/**
2761 * @ingroup Socket_register_access_function_W5100S
2762 * @brief Set @ref Sn_PORT register
2763 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2764 * @param (uint16_t)port Value to set @ref Sn_PORT.
2765 * @sa getSn_PORT()
2766 */
2767#define setSn_PORT(sn, port)  { \
2768                WIZCHIP_WRITE(Sn_PORT(sn),   (uint8_t)(port >> 8)); \
2769                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
2770        }
2771
2772/**
2773 * @ingroup Socket_register_access_function_W5100S
2774 * @brief Get @ref Sn_PORT register
2775 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2776 * @return uint16_t. Value of @ref Sn_PORT.
2777 * @sa setSn_PORT()
2778 */
2779#define getSn_PORT(sn) \
2780                (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
2781
2782/**
2783 * @ingroup Socket_register_access_function_W5100S
2784 * @brief Set @ref Sn_DHAR register
2785 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2786 * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
2787 * @sa getSn_DHAR()
2788 */
2789#define setSn_DHAR(sn, dhar) \
2790                WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
2791
2792/**
2793 * @ingroup Socket_register_access_function_W5100S
2794 * @brief Get @ref Sn_DHAR register
2795 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2796 * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
2797 * @sa setSn_DHAR()
2798 */
2799#define getSn_DHAR(sn, dhar) \
2800                WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
2801
2802/**
2803 * @ingroup Socket_register_access_function_W5100S
2804 * @brief Set @ref Sn_DIPR register
2805 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2806 * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
2807 * @sa getSn_DIPR()
2808 */
2809#define setSn_DIPR(sn, dipr) \
2810                WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
2811
2812/**
2813 * @ingroup Socket_register_access_function_W5100S
2814 * @brief Get @ref Sn_DIPR register
2815 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2816 * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
2817 * @sa SetSn_DIPR()
2818 */
2819#define getSn_DIPR(sn, dipr) \
2820                WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
2821
2822/**
2823 * @ingroup Socket_register_access_function_W5100S
2824 * @brief Set @ref Sn_DPORT register
2825 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2826 * @param (uint16_t)dport Value to set @ref Sn_DPORT
2827 * @sa getSn_DPORT()
2828 */
2829#define setSn_DPORT(sn, dport) { \
2830                WIZCHIP_WRITE(Sn_DPORT(sn),   (uint8_t) (dport>>8)); \
2831                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t)  dport); \
2832        }
2833
2834/**
2835 * @ingroup Socket_register_access_function_W5100S
2836 * @brief Get @ref Sn_DPORT register
2837 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2838 * @return uint16_t. Value of @ref Sn_DPORT.
2839 * @sa setSn_DPORT()
2840 */
2841#define getSn_DPORT(sn) \
2842                (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
2843
2844/**
2845 * @ingroup Socket_register_access_function_W5100S
2846 * @brief Set @ref Sn_MSSR register
2847 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2848 * @param (uint16_t)mss Value to set @ref Sn_MSSR
2849 * @sa setSn_MSSR()
2850 */
2851#define setSn_MSSR(sn, mss) { \
2852                WIZCHIP_WRITE(Sn_MSSR(sn),   (uint8_t)(mss>>8)); \
2853                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
2854        }
2855
2856/**
2857 * @ingroup Socket_register_access_function_W5100S
2858 * @brief Get @ref Sn_MSSR register
2859 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2860 * @return uint16_t. Value of @ref Sn_MSSR.
2861 * @sa setSn_MSSR()
2862 */
2863#define getSn_MSSR(sn) \
2864                (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
2865
2866/**
2867 * @ingroup Socket_register_access_function_W5100S
2868 * @brief Set @ref Sn_PROTO register
2869 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2870 * @param (uint8_t)proto Value to set \ref Sn_PROTO
2871 * @sa getSn_PROTO()
2872 */
2873#define setSn_PROTO(sn, proto) \
2874                WIZCHIP_WRITE(Sn_PROTO(sn), proto)
2875
2876/**
2877 * @ingroup Socket_register_access_function_W5100S
2878 * @brief Get @ref Sn_PROTO register
2879 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2880 * @return uint8_t. Value of @ref Sn_PROTO.
2881 * @sa setSn_PROTO()
2882 */
2883#define getSn_PROTO(sn) \
2884                WIZCHIP_READ(Sn_PROTO(sn))
2885
2886/**
2887 * @ingroup Socket_register_access_function_W5100S
2888 * @brief Set @ref Sn_TOS register
2889 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2890 * @param (uint8_t)tos Value to set @ref Sn_TOS
2891 * @sa getSn_TOS()
2892 */
2893#define setSn_TOS(sn, tos) \
2894                WIZCHIP_WRITE(Sn_TOS(sn), tos)
2895
2896/**
2897 * @ingroup Socket_register_access_function_W5100S
2898 * @brief Get @ref Sn_TOS register
2899 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_ </b>.
2900 * @return uint8_t. Value of Sn_TOS.
2901 * @sa setSn_TOS()
2902 */
2903#define getSn_TOS(sn) \
2904                WIZCHIP_READ(Sn_TOS(sn))
2905
2906/**
2907 * @ingroup Socket_register_access_function_W5100S
2908 * @brief Set @ref Sn_TTL register
2909 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_ </b>.
2910 * @param (uint8_t)ttl Value to set @ref Sn_TTL
2911 * @sa getSn_TTL()
2912 */
2913#define setSn_TTL(sn, ttl) \
2914                WIZCHIP_WRITE(Sn_TTL(sn), ttl)
2915
2916/**
2917 * @ingroup Socket_register_access_function_W5100S
2918 * @brief Get @ref Sn_TTL register
2919 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_ </b>.
2920 * @return uint8_t. Value of @ref Sn_TTL.
2921 * @sa setSn_TTL()
2922 */
2923#define getSn_TTL(sn) \
2924                WIZCHIP_READ(Sn_TTL(sn))
2925
2926/**
2927 * @ingroup Socket_register_access_function_W5100S
2928 * @brief Set @ref Sn_RXMEM_SIZE register
2929 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_ </b>.
2930 * @param (uint8_t)rxmemsize Value to set \ref Sn_RXMEM_SIZE
2931 * @sa getSn_RXMEM_SIZE()
2932 */
2933#define  setSn_RXMEM_SIZE(sn, rxmemsize) \
2934      WIZCHIP_WRITE(RMSR, (WIZCHIP_READ(RMSR) & ~(0x03 << (2*sn))) | (rxmemsize << (2*sn)))
2935#define setSn_RXBUF_SIZE(sn,rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
2936/**
2937 * @ingroup Socket_register_access_function_W5100S
2938 * @brief Get @ref Sn_RXMEM_SIZE register
2939 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2940 * @return uint8_t. Value of @ref Sn_RXMEM.
2941 * @sa setSn_RXMEM_SIZE()
2942 */
2943#define  getSn_RXMEM_SIZE(sn) \
2944      ((WIZCHIP_READ(RMSR) & (0x03 << (2*sn))) >> (2*sn))
2945#define  getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
2946
2947/**
2948 * @ingroup Socket_register_access_function_W5100S
2949 * @brief Set @ref Sn_TXMEM_SIZE register
2950 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2951 * @param (uint8_t)txmemsize Value to set \ref Sn_TXMEM_SIZE
2952 * @sa getSn_TXMEM_SIZE()
2953 */
2954#define setSn_TXMEM_SIZE(sn, txmemsize) \
2955      WIZCHIP_WRITE(TMSR, (WIZCHIP_READ(TMSR) & ~(0x03 << (2*sn))) | (txmemsize << (2*sn)))
2956#define  setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
2957
2958/**
2959 * @ingroup Socket_register_access_function_W5100S
2960 * @brief Get @ref Sn_TXMEM_SIZE register
2961 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2962 * @return uint8_t. Value of @ref Sn_TXMEM_SIZE.
2963 * @sa setSn_TXMEM_SIZE()
2964 */
2965#define  getSn_TXMEM_SIZE(sn) \
2966      ((WIZCHIP_READ(TMSR) & (0x03 << (2*sn))) >> (2*sn))
2967#define  getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
2968
2969/**
2970 * @ingroup Socket_register_access_function_W5100S
2971 * @brief Get @ref Sn_TX_FSR register
2972 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2973 * @return uint16_t. Value of @ref Sn_TX_FSR.
2974 */
2975uint16_t getSn_TX_FSR(uint8_t sn);
2976
2977/**
2978 * @ingroup Socket_register_access_function_W5100S
2979 * @brief Get @ref Sn_TX_RD register
2980 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2981 * @return uint16_t. Value of @ref Sn_TX_RD.
2982 */
2983#define getSn_TX_RD(sn) \
2984                (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
2985
2986/**
2987 * @ingroup Socket_register_access_function_W5100S
2988 * @brief Set @ref Sn_TX_WR register
2989 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
2990 * @param (uint16_t)txwr Value to set @ref Sn_TX_WR
2991 * @sa GetSn_TX_WR()
2992 */
2993#define setSn_TX_WR(sn, txwr) { \
2994                WIZCHIP_WRITE(Sn_TX_WR(sn),   (uint8_t)(txwr>>8)); \
2995                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
2996                }
2997
2998/**
2999 * @ingroup Socket_register_access_function_W5100S
3000 * @brief Get @ref Sn_TX_WR register
3001 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3002 * @return uint16_t. Value of @ref Sn_TX_WR.
3003 * @sa setSn_TX_WR()
3004 */
3005#define getSn_TX_WR(sn) \
3006                (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
3007
3008/**
3009 * @ingroup Socket_register_access_function_W5100S
3010 * @brief Get @ref Sn_RX_RSR register
3011 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3012 * @return uint16_t. Value of @ref Sn_RX_RSR.
3013 */
3014uint16_t getSn_RX_RSR(uint8_t sn);
3015
3016/**
3017 * @ingroup Socket_register_access_function_W5100S
3018 * @brief Set @ref Sn_RX_RD register
3019 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3020 * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD
3021 * @sa getSn_RX_RD()
3022 */
3023#define setSn_RX_RD(sn, rxrd) { \
3024                WIZCHIP_WRITE(Sn_RX_RD(sn),   (uint8_t)(rxrd>>8)); \
3025                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
3026        }
3027
3028/**
3029 * @ingroup Socket_register_access_function_W5100S
3030 * @brief Get @ref Sn_RX_RD register
3031 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3032 * @regurn uint16_t. Value of @ref Sn_RX_RD.
3033 * @sa setSn_RX_RD()
3034 */
3035#define getSn_RX_RD(sn) \
3036                (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
3037
3038/**
3039 * @ingroup Socket_register_access_function_W5100S
3040 * @brief Set @ref Sn_RX_WR register
3041 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3042 * @param (uint16_t)rxwr Value to set \ref Sn_RX_WR
3043 * @sa getSn_RX_WR()
3044 */
3045#define setSn_RX_WR(sn, rxwr) { \
3046                WIZCHIP_WRITE(Sn_RX_WR(sn),   (uint8_t)(rxwr>>8)); \
3047           WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
3048        }
3049
3050
3051/**
3052 * @ingroup Socket_register_access_function_W5100S
3053 * @brief Get @ref Sn_RX_WR register
3054 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3055 * @return uint16_t. Value of @ref Sn_RX_WR.
3056 */
3057#define getSn_RX_WR(sn) \
3058                (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
3059
3060/**
3061 * @ingroup Socket_register_access_function_W5100S
3062 * @brief Set @ref Sn_FRAGR register
3063 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3064 * @param (uint16_t)frag Value to set \ref Sn_FRAGR
3065 * @sa getSn_FRAG()
3066 */
3067#define setSn_FRAGR(sn, fragr) { \
3068                WIZCHIP_WRITE(Sn_FRAGR(sn),  (uint8_t)(fragr >>8)); \
3069                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAGR(sn),1), (uint8_t) fragr); \
3070        }
3071
3072/**
3073 * @ingroup Socket_register_access_function_W5100S
3074 * @brief Get @ref Sn_FRAGR register
3075 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3076 * @return uint16_t. Value of @ref Sn_FRAGR.
3077 * @sa setSn_FRAG()
3078 */
3079#define getSn_FRAGR(sn) \
3080                (((uint16_t)WIZCHIP_READ(Sn_FRAGR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAGR(sn),1)))
3081
3082/**
3083 * @ingroup Socket_register_access_function_W5100S
3084 * @brief Get the max RX buffer size of socket sn
3085 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3086 * @return uint16_t. Max buffer size
3087 */
3088#define getSn_RxMAX(sn) \
3089                ((uint16_t)(0x0001 << getSn_RXMEM_SIZE(sn)) << 10)
3090
3091
3092/**
3093 * @ingroup Socket_register_access_function_W5100S
3094 * @brief Get the max TX buffer size of socket sn
3095 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3096 * @return uint16_t. Max buffer size
3097 */
3098#define getSn_TxMAX(sn) \
3099                ((uint16_t)(0x0001 << getSn_TXMEM_SIZE(sn)) << 10)
3100
3101/**
3102 * @ingroup Socket_register_access_function_W5100S
3103 * @brief Get the mask of socket sn RX buffer.
3104 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3105 * @return uint16_t. Mask value
3106 */
3107#define getSn_RxMASK(sn) \
3108                (getSn_RxMAX(sn) - 1)
3109
3110/**
3111 * @ingroup Socket_register_access_function_W5100S
3112 * @brief Get the mask of socket sn TX buffer
3113 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3114 * @return uint16_t. Mask value
3115 */
3116#define getSn_TxMASK(sn) \
3117                (getSn_TxMAX(sn) - 1)
3118
3119
3120/**
3121 * @ingroup Socket_register_access_function_W5100S
3122 * @brief Get the base address of socket sn RX buffer.
3123 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3124 * @return uint16_t. Value of Socket n RX buffer base address.
3125 */
3126uint32_t getSn_RxBASE(uint8_t sn);
3127
3128/**
3129 * @ingroup Socket_register_access_function_W5100S
3130 * @brief Get the base address of socket sn TX buffer.
3131 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3132 * @return uint16_t. Value of Socket n TX buffer base address.
3133 */
3134uint32_t getSn_TxBASE(uint8_t sn);
3135
3136
3137/*socket register W5100S only*/
3138
3139/**
3140 * @ingroup Socket_register_access_function_W5100S
3141 * @brief Set the interrupt mask register of socket sn.
3142 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3143 * @param (uint16_t)imr Value to set \ref Sn_IMR
3144 * @sa getSn_IMR(sn)
3145 */
3146#define setSn_IMR(sn,imr)       \
3147                WIZCHIP_WRITE(Sn_IMR(sn),imr)
3148
3149/**
3150 * @ingroup Socket_register_access_function_W5100S
3151 * @brief Get the interrupt mask register of socket sn.
3152 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3153 * @return uint16_t. Value of Socket n interrupt mask register.
3154 */
3155#define getSn_IMR(sn)   \
3156                WIZCHIP_READ(Sn_IMR(sn))
3157
3158/**
3159 * @ingroup Socket_register_access_function_W5100S
3160 * @brief Set the Sn_MR2 value of socket sn.
3161 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3162 * @param mr2 Value of Sn_MR2 register to set.
3163 */
3164#define setSn_MR2(sn,mr2)       \
3165                WIZCHIP_WRITE(Sn_MR2(sn), mr2)
3166
3167/**
3168 * @ingroup Socket_register_access_function_W5100S
3169 * @brief Get the Sn_MR2 value of socket sn.
3170 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3171 * @return uint16_t. Value of Socket n Sn_MR2 register.
3172 */
3173#define getSn_MR2(sn)   \
3174                WIZCHIP_READ(Sn_MR2(sn))
3175
3176/**
3177 * @ingroup Socket_register_access_function_W5100S
3178 * @brief Set the Sn_KPALVTR value of socket sn.
3179 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3180 * @param kpalvtr Value of the Sn_KPALVTR register to set.
3181 */
3182#define setSn_KPALVTR(sn,kpalvtr)       \
3183                WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvtr)
3184
3185/**
3186 * @ingroup Socket_register_access_function_W5100S
3187 * @brief Get the Sn_KPALVTR value of socket sn
3188 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3189 * @return uint8_t. Value of the Sn_KPALVTR register.
3190 */
3191#define getSn_KPALVTR(sn)       \
3192                WIZCHIP_READ(Sn_KPALVTR(sn))
3193
3194/**
3195 * @ingroup Socket_register_access_function_W5100S
3196 * @brief Get the Sn_TSR register of socket sn.
3197 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3198 * @return uint8_t. Value of the Socket n Sn_TSR register.
3199 */
3200#define getSn_TSR(sn)   \
3201                WIZCHIP_READ(Sn_TSR(sn))
3202
3203/**
3204 * @ingroup Socket_register_access_function_W5100S
3205 * @brief Set the Sn_RTR register of socket sn.
3206 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3207 * @param (uint16_t)rtr Value of the Socket n Sn_RTR register to set.
3208 */
3209#define setSn_RTR(sn,rtr)       { \
3210                WIZCHIP_WRITE(Sn_RTR(sn),   (uint8_t)(rtr >> 8)); \
3211                WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RTR(sn),1), (uint8_t) rtr); \
3212                }
3213
3214/**
3215 * @ingroup Socket_register_access_function_W5100S
3216 * @brief Get the Sn_RTR register of socket sn.
3217 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3218 * @return uint16_t. Value of the Socket n Sn_RTR register.
3219 */
3220#define getSn_RTR(sn)   \
3221                (((uint16_t)WIZCHIP_READ(Sn_RTR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RTR(sn),1)))
3222
3223/**
3224 * @ingroup Socket_register_access_function_W5100S
3225 * @brief Set the Sn_RCR register of socket sn.
3226 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3227 * @return uint8_t. Value of the Socket n Sn_RCR register to set.
3228 */
3229#define setSn_RCR(sn,rcr)       \
3230                WIZCHIP_WRITE(Sn_RCR(sn),rcr)
3231
3232/**
3233 * @ingroup Socket_register_access_function_W5100S
3234 * @brief Get the Sn_RCR of socket sn.
3235 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3236 * @return uint8_t. Value of the Socket n Sn_RCR.
3237 */
3238#define getSn_RCR(sn)   \
3239                WIZCHIP_READ(Sn_RCR(sn))
3240
3241/////////////////////////////////////
3242// Sn_TXBUF & Sn_RXBUF IO function //
3243/////////////////////////////////////
3244/**
3245 * @ingroup Basic_IO_function_W5100S
3246 * @brief It copies data to internal TX memory
3247 *
3248 * @details This function reads the Tx write pointer register and after that,
3249 * it copies the <i>wizdata(pointer buffer)</i> of the length of <i>len(variable)</i> bytes to internal TX memory
3250 * and updates the Tx write pointer register.
3251 * This function is being called by send() and sendto() function also.
3252 *
3253 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3254 * @param wizdata Pointer buffer to write data
3255 * @param len Data length
3256 * @sa wiz_recv_data()
3257 */
3258void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
3259
3260/**
3261 * @ingroup Basic_IO_function_W5100S
3262 * @brief It copies data to your buffer from internal RX memory
3263 *
3264 * @details This function read the Rx read pointer register and after that,
3265 * it copies the received data from internal RX memory
3266 * to <i>wizdata(pointer variable)</i> of the length of <i>len(variable)</i> bytes.
3267 * This function is being called by recv() also.
3268 *
3269 * @param sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3270 * @param wizdata Pointer buffer to read data
3271 * @param len Data length
3272 * @sa wiz_send_data()
3273 */
3274void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
3275
3276/**
3277 * @ingroup Basic_IO_function_W5100S
3278 * @brief It discard the received data in RX memory.
3279 * @details It discards the data of the length of <i>len(variable)</i> bytes in internal RX memory.
3280 * @param (uint8_t)sn Socket number. It should be <b>0 ~ @ref \_WIZCHIP_SOCK_NUM_</b>.
3281 * @param len Data length
3282 */
3283void wiz_recv_ignore(uint8_t sn, uint16_t len);
3284
3285/**
3286 * @ingroup Special_function_W5100S
3287 * @brief Write data to the PHY via MDC/MDIO interface.
3288 * @details Write command data to the PHY via MDC/MDIO interface.
3289 * @param (uint8_t)PHYMDIO_regadr Address of the PHY register. It should be PHYMDIO_BMCR or PHYMDIO_BMSR.
3290 * @param (uint16_t)var Data to write to the PHY register. Please refer to the bit definitions of the BMCR and BMSR register.
3291 */
3292void wiz_mdio_write(uint8_t PHYMDIO_regadr, uint16_t var);
3293
3294/**
3295 * @ingroup Special_function_W5100S
3296 * @brief Read data from the PHY via MDC/MDIO interface.
3297 * @details Read command or status data from the PHY via MDC/MDIO interface.
3298 * @param (uint8_t)PHYMDIO_regadr Address of the PHY register. It should be PHYMDIO_BMCR or PHYMDIO_BMSR.
3299 * @return The value of the PHY register
3300 */
3301uint16_t wiz_mdio_read(uint8_t PHYMDIO_regadr);
3302
3303/**
3304 * @ingroup Special_function_W5100S
3305 * @brief Delay function
3306 * @details Delay function using internal 100us timer of the W5100S
3307 * @param (uint32_t)ms Time to delay in milliseconds.
3308 */
3309void wiz_delay_ms(uint32_t ms);
3310
3311/// @cond DOXY_APPLY_CODE
3312#endif
3313/// @endcond
3314
3315#ifdef __cplusplus
3316}
3317#endif
3318
3319#endif //_W5100S_H_
3320
3321
3322
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