Changeset 77 for ctrl/firmware/Main/CubeMX
- Timestamp:
- Feb 3, 2025, 3:27:37 PM (3 months ago)
- Location:
- ctrl/firmware/Main/CubeMX
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
ctrl/firmware/Main/CubeMX/Core/Inc/main.h
r76 r77 114 114 #define ETH_SPI_INT_Pin GPIO_PIN_8 115 115 #define ETH_SPI_INT_GPIO_Port GPIOB 116 #define ETH_SPI_INT_EXTI_IRQn EXTI9_5_IRQn 116 117 #define ETH_SPI_RST_Pin GPIO_PIN_9 117 118 #define ETH_SPI_RST_GPIO_Port GPIOB -
ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h
r72 r77 56 56 void DMA1_Stream1_IRQHandler(void); 57 57 void DMA1_Stream2_IRQHandler(void); 58 void EXTI9_5_IRQHandler(void); 58 59 void TIM3_IRQHandler(void); 60 void SPI2_IRQHandler(void); 59 61 void USART3_IRQHandler(void); 60 62 void TIM8_CC_IRQHandler(void); -
ctrl/firmware/Main/CubeMX/Core/Src/gpio.c
r76 r77 74 74 75 75 /*Configure GPIO pin Output Level */ 76 HAL_GPIO_WritePin(ETH_SPI_NSS_GPIO_Port, ETH_SPI_NSS_Pin, GPIO_PIN_SET); 77 78 /*Configure GPIO pin Output Level */ 76 79 HAL_GPIO_WritePin(ETH_SPI_RST_GPIO_Port, ETH_SPI_RST_Pin, GPIO_PIN_RESET); 77 80 … … 186 189 HAL_GPIO_Init(SD_DETECT_GPIO_Port, &GPIO_InitStruct); 187 190 191 /*Configure GPIO pins : ETH_SPI_NSS_Pin ETH_SPI_RST_Pin */ 192 GPIO_InitStruct.Pin = ETH_SPI_NSS_Pin|ETH_SPI_RST_Pin; 193 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 194 GPIO_InitStruct.Pull = GPIO_NOPULL; 195 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 196 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 197 188 198 /*Configure GPIO pin : ETH_SPI_INT_Pin */ 189 199 GPIO_InitStruct.Pin = ETH_SPI_INT_Pin; 190 GPIO_InitStruct.Mode = GPIO_MODE_IT_ RISING;200 GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 191 201 GPIO_InitStruct.Pull = GPIO_NOPULL; 192 202 HAL_GPIO_Init(ETH_SPI_INT_GPIO_Port, &GPIO_InitStruct); 193 203 194 /*Configure GPIO pin : ETH_SPI_RST_Pin */ 195 GPIO_InitStruct.Pin = ETH_SPI_RST_Pin; 196 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 197 GPIO_InitStruct.Pull = GPIO_NOPULL; 198 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 199 HAL_GPIO_Init(ETH_SPI_RST_GPIO_Port, &GPIO_InitStruct); 204 /* EXTI interrupt init*/ 205 HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 206 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 200 207 201 208 } -
ctrl/firmware/Main/CubeMX/Core/Src/main.c
r76 r77 35 35 #include <stdio.h> 36 36 37 #include "lwip.h"38 39 37 /* USER CODE END Includes */ 40 38 … … 187 185 RCC_OscInitStruct.PLL.PLLN = 40; 188 186 RCC_OscInitStruct.PLL.PLLP = 2; 189 RCC_OscInitStruct.PLL.PLLQ = 4;187 RCC_OscInitStruct.PLL.PLLQ = 2; 190 188 RCC_OscInitStruct.PLL.PLLR = 2; 191 189 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; -
ctrl/firmware/Main/CubeMX/Core/Src/spi.c
r76 r77 46 46 hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 47 47 hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 48 hspi2.Init.NSS = SPI_NSS_ HARD_OUTPUT;48 hspi2.Init.NSS = SPI_NSS_SOFT; 49 49 hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 50 50 hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; … … 57 57 hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 58 58 hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 59 hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_0 3CYCLE;60 hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_0 6CYCLE;59 hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 60 hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_01CYCLE; 61 61 hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 62 hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ ENABLE;62 hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 63 63 hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 64 64 if (HAL_SPI_Init(&hspi2) != HAL_OK) … … 128 128 */ 129 129 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI2; 130 PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; 130 PeriphClkInitStruct.PLL2.PLL2M = 2; 131 PeriphClkInitStruct.PLL2.PLL2N = 20; 132 PeriphClkInitStruct.PLL2.PLL2P = 2; 133 PeriphClkInitStruct.PLL2.PLL2Q = 11; 134 PeriphClkInitStruct.PLL2.PLL2R = 10; 135 PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 136 PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 137 PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 138 PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; 131 139 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 132 140 { … … 142 150 PB14 ------> SPI2_MISO 143 151 PB15 ------> SPI2_MOSI 144 PB4(NJTRST) ------> SPI2_NSS145 152 */ 146 153 GPIO_InitStruct.Pin = ETH_SPI_SCK_Pin|ETH_SPI_MISO_Pin|ETH_SPI_MOSI_Pin; … … 151 158 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 152 159 153 GPIO_InitStruct.Pin = ETH_SPI_NSS_Pin; 154 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 155 GPIO_InitStruct.Pull = GPIO_NOPULL; 156 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 157 GPIO_InitStruct.Alternate = GPIO_AF7_SPI2; 158 HAL_GPIO_Init(ETH_SPI_NSS_GPIO_Port, &GPIO_InitStruct); 159 160 /* SPI2 interrupt Init */ 161 HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0); 162 HAL_NVIC_EnableIRQ(SPI2_IRQn); 160 163 /* USER CODE BEGIN SPI2_MspInit 1 */ 161 164 … … 236 239 PB14 ------> SPI2_MISO 237 240 PB15 ------> SPI2_MOSI 238 PB4(NJTRST) ------> SPI2_NSS 239 */ 240 HAL_GPIO_DeInit(GPIOB, ETH_SPI_SCK_Pin|ETH_SPI_MISO_Pin|ETH_SPI_MOSI_Pin|ETH_SPI_NSS_Pin); 241 241 */ 242 HAL_GPIO_DeInit(GPIOB, ETH_SPI_SCK_Pin|ETH_SPI_MISO_Pin|ETH_SPI_MOSI_Pin); 243 244 /* SPI2 interrupt Deinit */ 245 HAL_NVIC_DisableIRQ(SPI2_IRQn); 242 246 /* USER CODE BEGIN SPI2_MspDeInit 1 */ 243 247 -
ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c
r72 r77 24 24 /* USER CODE BEGIN Includes */ 25 25 26 #include "FreeRTOS.h" 27 #include "semphr.h" 28 26 29 /* USER CODE END Includes */ 27 30 … … 59 62 extern SD_HandleTypeDef hsd1; 60 63 extern DMA_HandleTypeDef hdma_spi4_tx; 64 extern SPI_HandleTypeDef hspi2; 61 65 extern SPI_HandleTypeDef hspi4; 62 66 extern TIM_HandleTypeDef htim3; … … 212 216 213 217 /** 218 * @brief This function handles EXTI line[9:5] interrupts. 219 */ 220 void EXTI9_5_IRQHandler(void) 221 { 222 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ 223 224 /* USER CODE END EXTI9_5_IRQn 0 */ 225 HAL_GPIO_EXTI_IRQHandler(ETH_SPI_INT_Pin); 226 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ 227 228 /* USER CODE END EXTI9_5_IRQn 1 */ 229 } 230 231 /** 214 232 * @brief This function handles TIM3 global interrupt. 215 233 */ … … 226 244 227 245 /** 246 * @brief This function handles SPI2 global interrupt. 247 */ 248 void SPI2_IRQHandler(void) 249 { 250 /* USER CODE BEGIN SPI2_IRQn 0 */ 251 252 /* USER CODE END SPI2_IRQn 0 */ 253 HAL_SPI_IRQHandler(&hspi2); 254 /* USER CODE BEGIN SPI2_IRQn 1 */ 255 256 /* USER CODE END SPI2_IRQn 1 */ 257 } 258 259 /** 228 260 * @brief This function handles USART3 global interrupt. 229 261 */ … … 313 345 //------------------------------------------------------------------------------ 314 346 347 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef* hspi) 348 { 349 if (hspi->Instance == SPI2) 350 { 351 //HAL_GPIO_WritePin(ETH_SPI_NSS_GPIO_Port, ETH_SPI_NSS_Pin, GPIO_PIN_SET); 352 } 353 } 354 355 //------------------------------------------------------------------------------ 356 357 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) 358 { 359 if (GPIO_Pin == ETH_SPI_INT_Pin) 360 { 361 /*extern SemaphoreHandle_t s_xSemaphoreSpi; 362 363 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; 364 365 xSemaphoreGiveFromISR(s_xSemaphoreSpi, &xHigherPriorityTaskWoken);*/ 366 367 } 368 } 369 370 //------------------------------------------------------------------------------ 371 //------------------------------------------------------------------------------ 372 //------------------------------------------------------------------------------ 373 //------------------------------------------------------------------------------ 374 //------------------------------------------------------------------------------ 375 376 315 377 /* USER CODE END 1 */ -
ctrl/firmware/Main/CubeMX/charger.ioc
r76 r77 249 249 NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 250 250 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false 251 NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true 251 252 NVIC.ForceEnableDMAVector=true 252 253 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false … … 256 257 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 257 258 NVIC.SDMMC1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true 259 NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true 258 260 NVIC.SPI4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 259 261 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false … … 278 280 PA8.Locked=true 279 281 PA8.Signal=GPIO_Input 280 PB10.GPIOParameters=GPIO_ Label282 PB10.GPIOParameters=GPIO_Speed,GPIO_Label 281 283 PB10.GPIO_Label=ETH_SPI_SCK 284 PB10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 282 285 PB10.Mode=Full_Duplex_Master 283 286 PB10.Signal=SPI2_SCK 284 PB14.GPIOParameters=GPIO_ Label287 PB14.GPIOParameters=GPIO_Speed,GPIO_Label 285 288 PB14.GPIO_Label=ETH_SPI_MISO 289 PB14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 286 290 PB14.Locked=true 287 291 PB14.Mode=Full_Duplex_Master 288 292 PB14.Signal=SPI2_MISO 289 PB15.GPIOParameters=GPIO_ Label293 PB15.GPIOParameters=GPIO_Speed,GPIO_Label 290 294 PB15.GPIO_Label=ETH_SPI_MOSI 295 PB15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH 291 296 PB15.Locked=true 292 297 PB15.Mode=Full_Duplex_Master 293 298 PB15.Signal=SPI2_MOSI 294 PB4(NJTRST).GPIOParameters= GPIO_Label299 PB4(NJTRST).GPIOParameters=PinState,GPIO_Label 295 300 PB4(NJTRST).GPIO_Label=ETH_SPI_NSS 296 301 PB4(NJTRST).Locked=true 297 PB4(NJTRST). Mode=NSS_Signal_Hard_Output298 PB4(NJTRST).Signal= SPI2_NSS299 PB8.GPIOParameters=GPIO_Label 302 PB4(NJTRST).PinState=GPIO_PIN_SET 303 PB4(NJTRST).Signal=GPIO_Output 304 PB8.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI 300 305 PB8.GPIO_Label=ETH_SPI_INT 306 PB8.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING 301 307 PB8.Locked=true 302 308 PB8.Signal=GPXTI8 … … 462 468 ProjectManager.UnderRoot=true 463 469 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-MX_RTC_Init-RTC-false-HAL-true,4-MX_SPI4_Init-SPI4-false-HAL-true,5-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_TIM3_Init-TIM3-false-HAL-true,8-SystemClock_Config-RCC-false-HAL-false,9-MX_FATFS_Init-FATFS-false-HAL-false,10-MX_TIM8_Init-TIM8-false-HAL-true,11-MX_SPI2_Init-SPI2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true 464 RCC.ADCFreq_Value=1 66666666.66666666470 RCC.ADCFreq_Value=125000000 465 471 RCC.AHB12Freq_Value=100000000 466 472 RCC.AHB4Freq_Value=100000000 … … 475 481 RCC.CpuClockFreq_Value=100000000 476 482 RCC.D1CPREFreq_Value=100000000 477 RCC.DFSDMACLkFreq_Value= 50000000483 RCC.DFSDMACLkFreq_Value=100000000 478 484 RCC.DFSDMFreq_Value=100000000 479 485 RCC.DIVM1=5 480 RCC.DIVM2= 3486 RCC.DIVM2=2 481 487 RCC.DIVM3=25 482 488 RCC.DIVN1=40 483 RCC.DIVN2= 40489 RCC.DIVN2=20 484 490 RCC.DIVN3=200 485 491 RCC.DIVP1Freq_Value=100000000 486 RCC.DIVP2Freq_Value=1 66666666.66666666492 RCC.DIVP2Freq_Value=125000000 487 493 RCC.DIVP3Freq_Value=100000000 488 RCC.DIVQ1=4 489 RCC.DIVQ1Freq_Value=50000000 494 RCC.DIVQ1Freq_Value=100000000 490 495 RCC.DIVQ2=11 491 RCC.DIVQ2Freq_Value= 30303030.3030303496 RCC.DIVQ2Freq_Value=22727272.727272727 492 497 RCC.DIVQ3=8 493 498 RCC.DIVQ3Freq_Value=25000000 494 499 RCC.DIVR1Freq_Value=100000000 495 500 RCC.DIVR2=10 496 RCC.DIVR2Freq_Value= 33333333.333333332501 RCC.DIVR2Freq_Value=25000000 497 502 RCC.DIVR3Freq_Value=100000000 498 RCC.FDCANFreq_Value= 50000000503 RCC.FDCANFreq_Value=100000000 499 504 RCC.FMCFreq_Value=100000000 500 505 RCC.FamilyName=M … … 503 508 RCC.I2C123Freq_Value=100000000 504 509 RCC.I2C4Freq_Value=100000000 505 RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1 ,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value510 RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value 506 511 RCC.LPTIM1Freq_Value=100000000 507 512 RCC.LPTIM2Freq_Value=100000000 … … 518 523 RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE 519 524 RCC.RTCFreq_Value=32768 520 RCC.SAI1Freq_Value=50000000 521 RCC.SAI4AFreq_Value=50000000 522 RCC.SAI4BFreq_Value=50000000 523 RCC.SDMMCFreq_Value=50000000 524 RCC.SPDIFRXFreq_Value=50000000 525 RCC.SPI123Freq_Value=50000000 525 RCC.SAI1Freq_Value=100000000 526 RCC.SAI4AFreq_Value=100000000 527 RCC.SAI4BFreq_Value=100000000 528 RCC.SDMMCFreq_Value=100000000 529 RCC.SPDIFRXFreq_Value=100000000 530 RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL2 531 RCC.SPI123Freq_Value=125000000 526 532 RCC.SPI45Freq_Value=25000000 527 533 RCC.SPI6Freq_Value=100000000 … … 536 542 RCC.USART234578CLockSelection=RCC_USART234578CLKSOURCE_PLL3 537 543 RCC.USART234578Freq_Value=25000000 538 RCC.USBFreq_Value= 50000000544 RCC.USBFreq_Value=100000000 539 545 RCC.VCO1OutputFreq_Value=200000000 540 RCC.VCO2OutputFreq_Value= 333333333.3333333546 RCC.VCO2OutputFreq_Value=250000000 541 547 RCC.VCO3OutputFreq_Value=200000000 542 548 RCC.VCOInput1Freq_Value=5000000 543 RCC.VCOInput2Freq_Value= 8333333.333333333549 RCC.VCOInput2Freq_Value=12500000 544 550 RCC.VCOInput3Freq_Value=1000000 545 551 SDMMC1.ClockDiv=1 … … 554 560 SH.S_TIM8_CH1.1=TIM8_CH1,TriggerSource_TI1FP1 555 561 SH.S_TIM8_CH1.ConfNb=2 556 SPI2.CalculateBaudRate=25.0 MBits/s 562 SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2 563 SPI2.CalculateBaudRate=62.5 MBits/s 557 564 SPI2.DataSize=SPI_DATASIZE_8BIT 558 565 SPI2.Direction=SPI_DIRECTION_2LINES 559 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate, VirtualNSS,DataSize,MasterInterDataIdleness,MasterSSIdleness,MasterKeepIOState560 SPI2.MasterInterDataIdleness=SPI_MASTER_INTERDATA_IDLENESS_0 6CYCLE561 SPI2.MasterKeepIOState=SPI_MASTER_KEEP_IO_STATE_ ENABLE562 SPI2.MasterSSIdleness=SPI_MASTER_SS_IDLENESS_0 3CYCLE566 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,MasterInterDataIdleness,MasterSSIdleness,MasterKeepIOState,BaudRatePrescaler 567 SPI2.MasterInterDataIdleness=SPI_MASTER_INTERDATA_IDLENESS_01CYCLE 568 SPI2.MasterKeepIOState=SPI_MASTER_KEEP_IO_STATE_DISABLE 569 SPI2.MasterSSIdleness=SPI_MASTER_SS_IDLENESS_00CYCLE 563 570 SPI2.Mode=SPI_MODE_MASTER 564 SPI2.VirtualNSS=VM_NSSHARD565 571 SPI2.VirtualType=VM_MASTER 566 572 SPI4.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
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