source: trunk/firmware_v2/Drivers/CMSIS/Include/cmsis_armclang.h

Last change on this file was 17, checked in by f.jahn, 10 days ago
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[17]1/**************************************************************************//**
2 * @file     cmsis_armclang.h
3 * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
4 * @version  V5.4.3
5 * @date     27. May 2021
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
27#ifndef __CMSIS_ARMCLANG_H
28#define __CMSIS_ARMCLANG_H
29
30#pragma clang system_header   /* treat file as system include file */
31
32/* CMSIS compiler specific defines */
33#ifndef   __ASM
34  #define __ASM                                  __asm
35#endif
36#ifndef   __INLINE
37  #define __INLINE                               __inline
38#endif
39#ifndef   __STATIC_INLINE
40  #define __STATIC_INLINE                        static __inline
41#endif
42#ifndef   __STATIC_FORCEINLINE
43  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
44#endif
45#ifndef   __NO_RETURN
46  #define __NO_RETURN                            __attribute__((__noreturn__))
47#endif
48#ifndef   __USED
49  #define __USED                                 __attribute__((used))
50#endif
51#ifndef   __WEAK
52  #define __WEAK                                 __attribute__((weak))
53#endif
54#ifndef   __PACKED
55  #define __PACKED                               __attribute__((packed, aligned(1)))
56#endif
57#ifndef   __PACKED_STRUCT
58  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
59#endif
60#ifndef   __PACKED_UNION
61  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
62#endif
63#ifndef   __UNALIGNED_UINT32        /* deprecated */
64  #pragma clang diagnostic push
65  #pragma clang diagnostic ignored "-Wpacked"
66/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
67  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
68  #pragma clang diagnostic pop
69  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
70#endif
71#ifndef   __UNALIGNED_UINT16_WRITE
72  #pragma clang diagnostic push
73  #pragma clang diagnostic ignored "-Wpacked"
74/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
75  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
76  #pragma clang diagnostic pop
77  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
78#endif
79#ifndef   __UNALIGNED_UINT16_READ
80  #pragma clang diagnostic push
81  #pragma clang diagnostic ignored "-Wpacked"
82/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
83  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
84  #pragma clang diagnostic pop
85  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
86#endif
87#ifndef   __UNALIGNED_UINT32_WRITE
88  #pragma clang diagnostic push
89  #pragma clang diagnostic ignored "-Wpacked"
90/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
91  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
92  #pragma clang diagnostic pop
93  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
94#endif
95#ifndef   __UNALIGNED_UINT32_READ
96  #pragma clang diagnostic push
97  #pragma clang diagnostic ignored "-Wpacked"
98/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
99  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100  #pragma clang diagnostic pop
101  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102#endif
103#ifndef   __ALIGNED
104  #define __ALIGNED(x)                           __attribute__((aligned(x)))
105#endif
106#ifndef   __RESTRICT
107  #define __RESTRICT                             __restrict
108#endif
109#ifndef   __COMPILER_BARRIER
110  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
111#endif
112
113/* #########################  Startup and Lowlevel Init  ######################## */
114
115#ifndef __PROGRAM_START
116#define __PROGRAM_START           __main
117#endif
118
119#ifndef __INITIAL_SP
120#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
121#endif
122
123#ifndef __STACK_LIMIT
124#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
125#endif
126
127#ifndef __VECTOR_TABLE
128#define __VECTOR_TABLE            __Vectors
129#endif
130
131#ifndef __VECTOR_TABLE_ATTRIBUTE
132#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
133#endif
134
135#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
136#ifndef __STACK_SEAL
137#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base
138#endif
139
140#ifndef __TZ_STACK_SEAL_SIZE
141#define __TZ_STACK_SEAL_SIZE      8U
142#endif
143
144#ifndef __TZ_STACK_SEAL_VALUE
145#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
146#endif
147
148
149__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
150  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
151}
152#endif
153
154
155/* ##########################  Core Instruction Access  ######################### */
156/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
157  Access to dedicated instructions
158  @{
159*/
160
161/* Define macros for porting to both thumb1 and thumb2.
162 * For thumb1, use low register (r0-r7), specified by constraint "l"
163 * Otherwise, use general registers, specified by constraint "r" */
164#if defined (__thumb__) && !defined (__thumb2__)
165#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
166#define __CMSIS_GCC_RW_REG(r) "+l" (r)
167#define __CMSIS_GCC_USE_REG(r) "l" (r)
168#else
169#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
170#define __CMSIS_GCC_RW_REG(r) "+r" (r)
171#define __CMSIS_GCC_USE_REG(r) "r" (r)
172#endif
173
174/**
175  \brief   No Operation
176  \details No Operation does nothing. This instruction can be used for code alignment purposes.
177 */
178#define __NOP          __builtin_arm_nop
179
180/**
181  \brief   Wait For Interrupt
182  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
183 */
184#define __WFI          __builtin_arm_wfi
185
186
187/**
188  \brief   Wait For Event
189  \details Wait For Event is a hint instruction that permits the processor to enter
190           a low-power state until one of a number of events occurs.
191 */
192#define __WFE          __builtin_arm_wfe
193
194
195/**
196  \brief   Send Event
197  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
198 */
199#define __SEV          __builtin_arm_sev
200
201
202/**
203  \brief   Instruction Synchronization Barrier
204  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
205           so that all instructions following the ISB are fetched from cache or memory,
206           after the instruction has been completed.
207 */
208#define __ISB()        __builtin_arm_isb(0xF)
209
210/**
211  \brief   Data Synchronization Barrier
212  \details Acts as a special kind of Data Memory Barrier.
213           It completes when all explicit memory accesses before this instruction complete.
214 */
215#define __DSB()        __builtin_arm_dsb(0xF)
216
217
218/**
219  \brief   Data Memory Barrier
220  \details Ensures the apparent order of the explicit memory operations before
221           and after the instruction, without ensuring their completion.
222 */
223#define __DMB()        __builtin_arm_dmb(0xF)
224
225
226/**
227  \brief   Reverse byte order (32 bit)
228  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
229  \param [in]    value  Value to reverse
230  \return               Reversed value
231 */
232#define __REV(value)   __builtin_bswap32(value)
233
234
235/**
236  \brief   Reverse byte order (16 bit)
237  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
238  \param [in]    value  Value to reverse
239  \return               Reversed value
240 */
241#define __REV16(value) __ROR(__REV(value), 16)
242
243
244/**
245  \brief   Reverse byte order (16 bit)
246  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
247  \param [in]    value  Value to reverse
248  \return               Reversed value
249 */
250#define __REVSH(value) (int16_t)__builtin_bswap16(value)
251
252
253/**
254  \brief   Rotate Right in unsigned value (32 bit)
255  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
256  \param [in]    op1  Value to rotate
257  \param [in]    op2  Number of Bits to rotate
258  \return               Rotated value
259 */
260__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
261{
262  op2 %= 32U;
263  if (op2 == 0U)
264  {
265    return op1;
266  }
267  return (op1 >> op2) | (op1 << (32U - op2));
268}
269
270
271/**
272  \brief   Breakpoint
273  \details Causes the processor to enter Debug state.
274           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
275  \param [in]    value  is ignored by the processor.
276                 If required, a debugger can use it to store additional information about the breakpoint.
277 */
278#define __BKPT(value)     __ASM volatile ("bkpt "#value)
279
280
281/**
282  \brief   Reverse bit order of value
283  \details Reverses the bit order of the given value.
284  \param [in]    value  Value to reverse
285  \return               Reversed value
286 */
287#define __RBIT            __builtin_arm_rbit
288
289/**
290  \brief   Count leading zeros
291  \details Counts the number of leading zeros of a data value.
292  \param [in]  value  Value to count the leading zeros
293  \return             number of leading zeros in value
294 */
295__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
296{
297  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
298     __builtin_clz(0) is undefined behaviour, so handle this case specially.
299     This guarantees ARM-compatible results if happening to compile on a non-ARM
300     target, and ensures the compiler doesn't decide to activate any
301     optimisations using the logic "value was passed to __builtin_clz, so it
302     is non-zero".
303     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
304     single CLZ instruction.
305   */
306  if (value == 0U)
307  {
308    return 32U;
309  }
310  return __builtin_clz(value);
311}
312
313
314#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
315     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
316     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
317     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
318     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
319
320/**
321  \brief   LDR Exclusive (8 bit)
322  \details Executes a exclusive LDR instruction for 8 bit value.
323  \param [in]    ptr  Pointer to data
324  \return             value of type uint8_t at (*ptr)
325 */
326#define __LDREXB        (uint8_t)__builtin_arm_ldrex
327
328
329/**
330  \brief   LDR Exclusive (16 bit)
331  \details Executes a exclusive LDR instruction for 16 bit values.
332  \param [in]    ptr  Pointer to data
333  \return        value of type uint16_t at (*ptr)
334 */
335#define __LDREXH        (uint16_t)__builtin_arm_ldrex
336
337
338/**
339  \brief   LDR Exclusive (32 bit)
340  \details Executes a exclusive LDR instruction for 32 bit values.
341  \param [in]    ptr  Pointer to data
342  \return        value of type uint32_t at (*ptr)
343 */
344#define __LDREXW        (uint32_t)__builtin_arm_ldrex
345
346
347/**
348  \brief   STR Exclusive (8 bit)
349  \details Executes a exclusive STR instruction for 8 bit values.
350  \param [in]  value  Value to store
351  \param [in]    ptr  Pointer to location
352  \return          0  Function succeeded
353  \return          1  Function failed
354 */
355#define __STREXB        (uint32_t)__builtin_arm_strex
356
357
358/**
359  \brief   STR Exclusive (16 bit)
360  \details Executes a exclusive STR instruction for 16 bit values.
361  \param [in]  value  Value to store
362  \param [in]    ptr  Pointer to location
363  \return          0  Function succeeded
364  \return          1  Function failed
365 */
366#define __STREXH        (uint32_t)__builtin_arm_strex
367
368
369/**
370  \brief   STR Exclusive (32 bit)
371  \details Executes a exclusive STR instruction for 32 bit values.
372  \param [in]  value  Value to store
373  \param [in]    ptr  Pointer to location
374  \return          0  Function succeeded
375  \return          1  Function failed
376 */
377#define __STREXW        (uint32_t)__builtin_arm_strex
378
379
380/**
381  \brief   Remove the exclusive lock
382  \details Removes the exclusive lock which is created by LDREX.
383 */
384#define __CLREX             __builtin_arm_clrex
385
386#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
387           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
388           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
389           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
390           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
391
392
393#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
394     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
395     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
396     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
397
398/**
399  \brief   Signed Saturate
400  \details Saturates a signed value.
401  \param [in]  value  Value to be saturated
402  \param [in]    sat  Bit position to saturate to (1..32)
403  \return             Saturated value
404 */
405#define __SSAT             __builtin_arm_ssat
406
407
408/**
409  \brief   Unsigned Saturate
410  \details Saturates an unsigned value.
411  \param [in]  value  Value to be saturated
412  \param [in]    sat  Bit position to saturate to (0..31)
413  \return             Saturated value
414 */
415#define __USAT             __builtin_arm_usat
416
417
418/**
419  \brief   Rotate Right with Extend (32 bit)
420  \details Moves each bit of a bitstring right by one bit.
421           The carry input is shifted in at the left end of the bitstring.
422  \param [in]    value  Value to rotate
423  \return               Rotated value
424 */
425__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
426{
427  uint32_t result;
428
429  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
430  return(result);
431}
432
433
434/**
435  \brief   LDRT Unprivileged (8 bit)
436  \details Executes a Unprivileged LDRT instruction for 8 bit value.
437  \param [in]    ptr  Pointer to data
438  \return             value of type uint8_t at (*ptr)
439 */
440__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
441{
442  uint32_t result;
443
444  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
445  return ((uint8_t) result);    /* Add explicit type cast here */
446}
447
448
449/**
450  \brief   LDRT Unprivileged (16 bit)
451  \details Executes a Unprivileged LDRT instruction for 16 bit values.
452  \param [in]    ptr  Pointer to data
453  \return        value of type uint16_t at (*ptr)
454 */
455__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
456{
457  uint32_t result;
458
459  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
460  return ((uint16_t) result);    /* Add explicit type cast here */
461}
462
463
464/**
465  \brief   LDRT Unprivileged (32 bit)
466  \details Executes a Unprivileged LDRT instruction for 32 bit values.
467  \param [in]    ptr  Pointer to data
468  \return        value of type uint32_t at (*ptr)
469 */
470__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
471{
472  uint32_t result;
473
474  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
475  return(result);
476}
477
478
479/**
480  \brief   STRT Unprivileged (8 bit)
481  \details Executes a Unprivileged STRT instruction for 8 bit values.
482  \param [in]  value  Value to store
483  \param [in]    ptr  Pointer to location
484 */
485__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
486{
487  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
488}
489
490
491/**
492  \brief   STRT Unprivileged (16 bit)
493  \details Executes a Unprivileged STRT instruction for 16 bit values.
494  \param [in]  value  Value to store
495  \param [in]    ptr  Pointer to location
496 */
497__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
498{
499  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
500}
501
502
503/**
504  \brief   STRT Unprivileged (32 bit)
505  \details Executes a Unprivileged STRT instruction for 32 bit values.
506  \param [in]  value  Value to store
507  \param [in]    ptr  Pointer to location
508 */
509__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
510{
511  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
512}
513
514#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
515          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
516          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
517          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
518
519/**
520  \brief   Signed Saturate
521  \details Saturates a signed value.
522  \param [in]  value  Value to be saturated
523  \param [in]    sat  Bit position to saturate to (1..32)
524  \return             Saturated value
525 */
526__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
527{
528  if ((sat >= 1U) && (sat <= 32U))
529  {
530    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
531    const int32_t min = -1 - max ;
532    if (val > max)
533    {
534      return max;
535    }
536    else if (val < min)
537    {
538      return min;
539    }
540  }
541  return val;
542}
543
544/**
545  \brief   Unsigned Saturate
546  \details Saturates an unsigned value.
547  \param [in]  value  Value to be saturated
548  \param [in]    sat  Bit position to saturate to (0..31)
549  \return             Saturated value
550 */
551__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
552{
553  if (sat <= 31U)
554  {
555    const uint32_t max = ((1U << sat) - 1U);
556    if (val > (int32_t)max)
557    {
558      return max;
559    }
560    else if (val < 0)
561    {
562      return 0U;
563    }
564  }
565  return (uint32_t)val;
566}
567
568#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
569           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
570           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
571           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
572
573
574#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
575     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
576     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
577
578/**
579  \brief   Load-Acquire (8 bit)
580  \details Executes a LDAB instruction for 8 bit value.
581  \param [in]    ptr  Pointer to data
582  \return             value of type uint8_t at (*ptr)
583 */
584__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
585{
586  uint32_t result;
587
588  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
589  return ((uint8_t) result);
590}
591
592
593/**
594  \brief   Load-Acquire (16 bit)
595  \details Executes a LDAH instruction for 16 bit values.
596  \param [in]    ptr  Pointer to data
597  \return        value of type uint16_t at (*ptr)
598 */
599__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
600{
601  uint32_t result;
602
603  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
604  return ((uint16_t) result);
605}
606
607
608/**
609  \brief   Load-Acquire (32 bit)
610  \details Executes a LDA instruction for 32 bit values.
611  \param [in]    ptr  Pointer to data
612  \return        value of type uint32_t at (*ptr)
613 */
614__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
615{
616  uint32_t result;
617
618  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
619  return(result);
620}
621
622
623/**
624  \brief   Store-Release (8 bit)
625  \details Executes a STLB instruction for 8 bit values.
626  \param [in]  value  Value to store
627  \param [in]    ptr  Pointer to location
628 */
629__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
630{
631  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
632}
633
634
635/**
636  \brief   Store-Release (16 bit)
637  \details Executes a STLH instruction for 16 bit values.
638  \param [in]  value  Value to store
639  \param [in]    ptr  Pointer to location
640 */
641__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
642{
643  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
644}
645
646
647/**
648  \brief   Store-Release (32 bit)
649  \details Executes a STL instruction for 32 bit values.
650  \param [in]  value  Value to store
651  \param [in]    ptr  Pointer to location
652 */
653__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
654{
655  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
656}
657
658
659/**
660  \brief   Load-Acquire Exclusive (8 bit)
661  \details Executes a LDAB exclusive instruction for 8 bit value.
662  \param [in]    ptr  Pointer to data
663  \return             value of type uint8_t at (*ptr)
664 */
665#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
666
667
668/**
669  \brief   Load-Acquire Exclusive (16 bit)
670  \details Executes a LDAH exclusive instruction for 16 bit values.
671  \param [in]    ptr  Pointer to data
672  \return        value of type uint16_t at (*ptr)
673 */
674#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
675
676
677/**
678  \brief   Load-Acquire Exclusive (32 bit)
679  \details Executes a LDA exclusive instruction for 32 bit values.
680  \param [in]    ptr  Pointer to data
681  \return        value of type uint32_t at (*ptr)
682 */
683#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
684
685
686/**
687  \brief   Store-Release Exclusive (8 bit)
688  \details Executes a STLB exclusive instruction for 8 bit values.
689  \param [in]  value  Value to store
690  \param [in]    ptr  Pointer to location
691  \return          0  Function succeeded
692  \return          1  Function failed
693 */
694#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
695
696
697/**
698  \brief   Store-Release Exclusive (16 bit)
699  \details Executes a STLH exclusive instruction for 16 bit values.
700  \param [in]  value  Value to store
701  \param [in]    ptr  Pointer to location
702  \return          0  Function succeeded
703  \return          1  Function failed
704 */
705#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
706
707
708/**
709  \brief   Store-Release Exclusive (32 bit)
710  \details Executes a STL exclusive instruction for 32 bit values.
711  \param [in]  value  Value to store
712  \param [in]    ptr  Pointer to location
713  \return          0  Function succeeded
714  \return          1  Function failed
715 */
716#define     __STLEX                  (uint32_t)__builtin_arm_stlex
717
718#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
719           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
720           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
721
722/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
723
724
725/* ###########################  Core Function Access  ########################### */
726/** \ingroup  CMSIS_Core_FunctionInterface
727    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
728  @{
729 */
730
731/**
732  \brief   Enable IRQ Interrupts
733  \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
734           Can only be executed in Privileged modes.
735 */
736#ifndef __ARM_COMPAT_H
737__STATIC_FORCEINLINE void __enable_irq(void)
738{
739  __ASM volatile ("cpsie i" : : : "memory");
740}
741#endif
742
743
744/**
745  \brief   Disable IRQ Interrupts
746  \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
747           Can only be executed in Privileged modes.
748 */
749#ifndef __ARM_COMPAT_H
750__STATIC_FORCEINLINE void __disable_irq(void)
751{
752  __ASM volatile ("cpsid i" : : : "memory");
753}
754#endif
755
756
757/**
758  \brief   Get Control Register
759  \details Returns the content of the Control Register.
760  \return               Control Register value
761 */
762__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
763{
764  uint32_t result;
765
766  __ASM volatile ("MRS %0, control" : "=r" (result) );
767  return(result);
768}
769
770
771#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
772/**
773  \brief   Get Control Register (non-secure)
774  \details Returns the content of the non-secure Control Register when in secure mode.
775  \return               non-secure Control Register value
776 */
777__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
778{
779  uint32_t result;
780
781  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
782  return(result);
783}
784#endif
785
786
787/**
788  \brief   Set Control Register
789  \details Writes the given value to the Control Register.
790  \param [in]    control  Control Register value to set
791 */
792__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
793{
794  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
795  __ISB();
796}
797
798
799#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
800/**
801  \brief   Set Control Register (non-secure)
802  \details Writes the given value to the non-secure Control Register when in secure state.
803  \param [in]    control  Control Register value to set
804 */
805__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
806{
807  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
808  __ISB();
809}
810#endif
811
812
813/**
814  \brief   Get IPSR Register
815  \details Returns the content of the IPSR Register.
816  \return               IPSR Register value
817 */
818__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
819{
820  uint32_t result;
821
822  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
823  return(result);
824}
825
826
827/**
828  \brief   Get APSR Register
829  \details Returns the content of the APSR Register.
830  \return               APSR Register value
831 */
832__STATIC_FORCEINLINE uint32_t __get_APSR(void)
833{
834  uint32_t result;
835
836  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
837  return(result);
838}
839
840
841/**
842  \brief   Get xPSR Register
843  \details Returns the content of the xPSR Register.
844  \return               xPSR Register value
845 */
846__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
847{
848  uint32_t result;
849
850  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
851  return(result);
852}
853
854
855/**
856  \brief   Get Process Stack Pointer
857  \details Returns the current value of the Process Stack Pointer (PSP).
858  \return               PSP Register value
859 */
860__STATIC_FORCEINLINE uint32_t __get_PSP(void)
861{
862  uint32_t result;
863
864  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
865  return(result);
866}
867
868
869#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
870/**
871  \brief   Get Process Stack Pointer (non-secure)
872  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
873  \return               PSP Register value
874 */
875__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
876{
877  uint32_t result;
878
879  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
880  return(result);
881}
882#endif
883
884
885/**
886  \brief   Set Process Stack Pointer
887  \details Assigns the given value to the Process Stack Pointer (PSP).
888  \param [in]    topOfProcStack  Process Stack Pointer value to set
889 */
890__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
891{
892  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
893}
894
895
896#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
897/**
898  \brief   Set Process Stack Pointer (non-secure)
899  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
900  \param [in]    topOfProcStack  Process Stack Pointer value to set
901 */
902__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
903{
904  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
905}
906#endif
907
908
909/**
910  \brief   Get Main Stack Pointer
911  \details Returns the current value of the Main Stack Pointer (MSP).
912  \return               MSP Register value
913 */
914__STATIC_FORCEINLINE uint32_t __get_MSP(void)
915{
916  uint32_t result;
917
918  __ASM volatile ("MRS %0, msp" : "=r" (result) );
919  return(result);
920}
921
922
923#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
924/**
925  \brief   Get Main Stack Pointer (non-secure)
926  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
927  \return               MSP Register value
928 */
929__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
930{
931  uint32_t result;
932
933  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
934  return(result);
935}
936#endif
937
938
939/**
940  \brief   Set Main Stack Pointer
941  \details Assigns the given value to the Main Stack Pointer (MSP).
942  \param [in]    topOfMainStack  Main Stack Pointer value to set
943 */
944__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
945{
946  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
947}
948
949
950#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
951/**
952  \brief   Set Main Stack Pointer (non-secure)
953  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
954  \param [in]    topOfMainStack  Main Stack Pointer value to set
955 */
956__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
957{
958  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
959}
960#endif
961
962
963#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
964/**
965  \brief   Get Stack Pointer (non-secure)
966  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
967  \return               SP Register value
968 */
969__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
970{
971  uint32_t result;
972
973  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
974  return(result);
975}
976
977
978/**
979  \brief   Set Stack Pointer (non-secure)
980  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
981  \param [in]    topOfStack  Stack Pointer value to set
982 */
983__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
984{
985  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
986}
987#endif
988
989
990/**
991  \brief   Get Priority Mask
992  \details Returns the current state of the priority mask bit from the Priority Mask Register.
993  \return               Priority Mask value
994 */
995__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
996{
997  uint32_t result;
998
999  __ASM volatile ("MRS %0, primask" : "=r" (result) );
1000  return(result);
1001}
1002
1003
1004#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1005/**
1006  \brief   Get Priority Mask (non-secure)
1007  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
1008  \return               Priority Mask value
1009 */
1010__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1011{
1012  uint32_t result;
1013
1014  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1015  return(result);
1016}
1017#endif
1018
1019
1020/**
1021  \brief   Set Priority Mask
1022  \details Assigns the given value to the Priority Mask Register.
1023  \param [in]    priMask  Priority Mask
1024 */
1025__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1026{
1027  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1028}
1029
1030
1031#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1032/**
1033  \brief   Set Priority Mask (non-secure)
1034  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1035  \param [in]    priMask  Priority Mask
1036 */
1037__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1038{
1039  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1040}
1041#endif
1042
1043
1044#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
1045     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
1046     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1047     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
1048/**
1049  \brief   Enable FIQ
1050  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1051           Can only be executed in Privileged modes.
1052 */
1053__STATIC_FORCEINLINE void __enable_fault_irq(void)
1054{
1055  __ASM volatile ("cpsie f" : : : "memory");
1056}
1057
1058
1059/**
1060  \brief   Disable FIQ
1061  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1062           Can only be executed in Privileged modes.
1063 */
1064__STATIC_FORCEINLINE void __disable_fault_irq(void)
1065{
1066  __ASM volatile ("cpsid f" : : : "memory");
1067}
1068
1069
1070/**
1071  \brief   Get Base Priority
1072  \details Returns the current value of the Base Priority register.
1073  \return               Base Priority register value
1074 */
1075__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1076{
1077  uint32_t result;
1078
1079  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1080  return(result);
1081}
1082
1083
1084#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1085/**
1086  \brief   Get Base Priority (non-secure)
1087  \details Returns the current value of the non-secure Base Priority register when in secure state.
1088  \return               Base Priority register value
1089 */
1090__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1091{
1092  uint32_t result;
1093
1094  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1095  return(result);
1096}
1097#endif
1098
1099
1100/**
1101  \brief   Set Base Priority
1102  \details Assigns the given value to the Base Priority register.
1103  \param [in]    basePri  Base Priority value to set
1104 */
1105__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1106{
1107  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1108}
1109
1110
1111#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1112/**
1113  \brief   Set Base Priority (non-secure)
1114  \details Assigns the given value to the non-secure Base Priority register when in secure state.
1115  \param [in]    basePri  Base Priority value to set
1116 */
1117__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1118{
1119  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1120}
1121#endif
1122
1123
1124/**
1125  \brief   Set Base Priority with condition
1126  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1127           or the new value increases the BASEPRI priority level.
1128  \param [in]    basePri  Base Priority value to set
1129 */
1130__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1131{
1132  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1133}
1134
1135
1136/**
1137  \brief   Get Fault Mask
1138  \details Returns the current value of the Fault Mask register.
1139  \return               Fault Mask register value
1140 */
1141__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1142{
1143  uint32_t result;
1144
1145  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1146  return(result);
1147}
1148
1149
1150#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1151/**
1152  \brief   Get Fault Mask (non-secure)
1153  \details Returns the current value of the non-secure Fault Mask register when in secure state.
1154  \return               Fault Mask register value
1155 */
1156__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1157{
1158  uint32_t result;
1159
1160  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1161  return(result);
1162}
1163#endif
1164
1165
1166/**
1167  \brief   Set Fault Mask
1168  \details Assigns the given value to the Fault Mask register.
1169  \param [in]    faultMask  Fault Mask value to set
1170 */
1171__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1172{
1173  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1174}
1175
1176
1177#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1178/**
1179  \brief   Set Fault Mask (non-secure)
1180  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1181  \param [in]    faultMask  Fault Mask value to set
1182 */
1183__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1184{
1185  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1186}
1187#endif
1188
1189#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \
1190           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \
1191           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1192           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
1193
1194
1195#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1196     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
1197     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )
1198
1199/**
1200  \brief   Get Process Stack Pointer Limit
1201  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1202  Stack Pointer Limit register hence zero is returned always in non-secure
1203  mode.
1204
1205  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1206  \return               PSPLIM Register value
1207 */
1208__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1209{
1210#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1211       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
1212    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1213    // without main extensions, the non-secure PSPLIM is RAZ/WI
1214  return 0U;
1215#else
1216  uint32_t result;
1217  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
1218  return result;
1219#endif
1220}
1221
1222#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1223/**
1224  \brief   Get Process Stack Pointer Limit (non-secure)
1225  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1226  Stack Pointer Limit register hence zero is returned always in non-secure
1227  mode.
1228
1229  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1230  \return               PSPLIM Register value
1231 */
1232__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1233{
1234#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1235       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
1236  // without main extensions, the non-secure PSPLIM is RAZ/WI
1237  return 0U;
1238#else
1239  uint32_t result;
1240  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
1241  return result;
1242#endif
1243}
1244#endif
1245
1246
1247/**
1248  \brief   Set Process Stack Pointer Limit
1249  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1250  Stack Pointer Limit register hence the write is silently ignored in non-secure
1251  mode.
1252
1253  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1254  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
1255 */
1256__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1257{
1258#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1259       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
1260    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1261  // without main extensions, the non-secure PSPLIM is RAZ/WI
1262  (void)ProcStackPtrLimit;
1263#else
1264  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1265#endif
1266}
1267
1268
1269#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
1270/**
1271  \brief   Set Process Stack Pointer (non-secure)
1272  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1273  Stack Pointer Limit register hence the write is silently ignored in non-secure
1274  mode.
1275
1276  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1277  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
1278 */
1279__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1280{
1281#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1282       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
1283  // without main extensions, the non-secure PSPLIM is RAZ/WI
1284  (void)ProcStackPtrLimit;
1285#else
1286  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1287#endif
1288}
1289#endif
1290
1291
1292/**
1293  \brief   Get Main Stack Pointer Limit
1294  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1295  Stack Pointer Limit register hence zero is returned always.
1296
1297  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1298  \return               MSPLIM Register value
1299 */
1300__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1301{
1302#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1303       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
1304    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1305  // without main extensions, the non-secure MSPLIM is RAZ/WI
1306  return 0U;
1307#else
1308  uint32_t result;
1309  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1310  return result;
1311#endif
1312}
1313
1314
1315#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
1316/**
1317  \brief   Get Main Stack Pointer Limit (non-secure)
1318  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1319  Stack Pointer Limit register hence zero is returned always.
1320
1321  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1322  \return               MSPLIM Register value
1323 */
1324__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1325{
1326#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1327       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
1328  // without main extensions, the non-secure MSPLIM is RAZ/WI
1329  return 0U;
1330#else
1331  uint32_t result;
1332  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1333  return result;
1334#endif
1335}
1336#endif
1337
1338
1339/**
1340  \brief   Set Main Stack Pointer Limit
1341  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1342  Stack Pointer Limit register hence the write is silently ignored.
1343
1344  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1345  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
1346 */
1347__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1348{
1349#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1350       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \
1351    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1352  // without main extensions, the non-secure MSPLIM is RAZ/WI
1353  (void)MainStackPtrLimit;
1354#else
1355  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1356#endif
1357}
1358
1359
1360#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
1361/**
1362  \brief   Set Main Stack Pointer Limit (non-secure)
1363  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1364  Stack Pointer Limit register hence the write is silently ignored.
1365
1366  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1367  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
1368 */
1369__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1370{
1371#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1372       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )
1373  // without main extensions, the non-secure MSPLIM is RAZ/WI
1374  (void)MainStackPtrLimit;
1375#else
1376  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1377#endif
1378}
1379#endif
1380
1381#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \
1382           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \
1383           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */
1384
1385/**
1386  \brief   Get FPSCR
1387  \details Returns the current value of the Floating Point Status/Control register.
1388  \return               Floating Point Status/Control register value
1389 */
1390#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1391     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
1392#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
1393#else
1394#define __get_FPSCR()      ((uint32_t)0U)
1395#endif
1396
1397/**
1398  \brief   Set FPSCR
1399  \details Assigns the given value to the Floating Point Status/Control register.
1400  \param [in]    fpscr  Floating Point Status/Control value to set
1401 */
1402#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1403     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
1404#define __set_FPSCR      __builtin_arm_set_fpscr
1405#else
1406#define __set_FPSCR(x)      ((void)(x))
1407#endif
1408
1409
1410/*@} end of CMSIS_Core_RegAccFunctions */
1411
1412
1413/* ###################  Compiler specific Intrinsics  ########################### */
1414/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1415  Access to dedicated SIMD instructions
1416  @{
1417*/
1418
1419#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1420
1421#define     __SADD8                 __builtin_arm_sadd8
1422#define     __QADD8                 __builtin_arm_qadd8
1423#define     __SHADD8                __builtin_arm_shadd8
1424#define     __UADD8                 __builtin_arm_uadd8
1425#define     __UQADD8                __builtin_arm_uqadd8
1426#define     __UHADD8                __builtin_arm_uhadd8
1427#define     __SSUB8                 __builtin_arm_ssub8
1428#define     __QSUB8                 __builtin_arm_qsub8
1429#define     __SHSUB8                __builtin_arm_shsub8
1430#define     __USUB8                 __builtin_arm_usub8
1431#define     __UQSUB8                __builtin_arm_uqsub8
1432#define     __UHSUB8                __builtin_arm_uhsub8
1433#define     __SADD16                __builtin_arm_sadd16
1434#define     __QADD16                __builtin_arm_qadd16
1435#define     __SHADD16               __builtin_arm_shadd16
1436#define     __UADD16                __builtin_arm_uadd16
1437#define     __UQADD16               __builtin_arm_uqadd16
1438#define     __UHADD16               __builtin_arm_uhadd16
1439#define     __SSUB16                __builtin_arm_ssub16
1440#define     __QSUB16                __builtin_arm_qsub16
1441#define     __SHSUB16               __builtin_arm_shsub16
1442#define     __USUB16                __builtin_arm_usub16
1443#define     __UQSUB16               __builtin_arm_uqsub16
1444#define     __UHSUB16               __builtin_arm_uhsub16
1445#define     __SASX                  __builtin_arm_sasx
1446#define     __QASX                  __builtin_arm_qasx
1447#define     __SHASX                 __builtin_arm_shasx
1448#define     __UASX                  __builtin_arm_uasx
1449#define     __UQASX                 __builtin_arm_uqasx
1450#define     __UHASX                 __builtin_arm_uhasx
1451#define     __SSAX                  __builtin_arm_ssax
1452#define     __QSAX                  __builtin_arm_qsax
1453#define     __SHSAX                 __builtin_arm_shsax
1454#define     __USAX                  __builtin_arm_usax
1455#define     __UQSAX                 __builtin_arm_uqsax
1456#define     __UHSAX                 __builtin_arm_uhsax
1457#define     __USAD8                 __builtin_arm_usad8
1458#define     __USADA8                __builtin_arm_usada8
1459#define     __SSAT16                __builtin_arm_ssat16
1460#define     __USAT16                __builtin_arm_usat16
1461#define     __UXTB16                __builtin_arm_uxtb16
1462#define     __UXTAB16               __builtin_arm_uxtab16
1463#define     __SXTB16                __builtin_arm_sxtb16
1464#define     __SXTAB16               __builtin_arm_sxtab16
1465#define     __SMUAD                 __builtin_arm_smuad
1466#define     __SMUADX                __builtin_arm_smuadx
1467#define     __SMLAD                 __builtin_arm_smlad
1468#define     __SMLADX                __builtin_arm_smladx
1469#define     __SMLALD                __builtin_arm_smlald
1470#define     __SMLALDX               __builtin_arm_smlaldx
1471#define     __SMUSD                 __builtin_arm_smusd
1472#define     __SMUSDX                __builtin_arm_smusdx
1473#define     __SMLSD                 __builtin_arm_smlsd
1474#define     __SMLSDX                __builtin_arm_smlsdx
1475#define     __SMLSLD                __builtin_arm_smlsld
1476#define     __SMLSLDX               __builtin_arm_smlsldx
1477#define     __SEL                   __builtin_arm_sel
1478#define     __QADD                  __builtin_arm_qadd
1479#define     __QSUB                  __builtin_arm_qsub
1480
1481#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
1482                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
1483
1484#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
1485                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
1486
1487#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
1488
1489#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1490
1491__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1492{
1493  int32_t result;
1494
1495  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
1496  return(result);
1497}
1498
1499#endif /* (__ARM_FEATURE_DSP == 1) */
1500/*@} end of group CMSIS_SIMD_intrinsics */
1501
1502
1503#endif /* __CMSIS_ARMCLANG_H */
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