source: trunk/firmware/Drivers/CMSIS/Include/core_cm0.h

Last change on this file was 6, checked in by f.jahn, 3 months ago
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1/**************************************************************************//**
2 * @file     core_cm0.h
3 * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version  V5.0.6
5 * @date     13. March 2019
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if   defined ( __ICCARM__ )
26  #pragma system_include         /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28  #pragma clang system_header   /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM0_H_GENERIC
32#define __CORE_CM0_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
42  CMSIS violates the following MISRA-C:2004 rules:
43
44   \li Required Rule 8.5, object/function definition in header file.<br>
45     Function definitions in header files are used to allow 'inlining'.
46
47   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48     Unions are used for effective representation of core registers.
49
50   \li Advisory Rule 19.7, Function-like macro defined.<br>
51     Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 *                 CMSIS definitions
57 ******************************************************************************/
58/**
59  \ingroup Cortex_M0
60  @{
61 */
62
63#include "cmsis_version.h"
64 
65/*  CMSIS CM0 definitions */
66#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
68#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
69                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74    This core does not support an FPU at all
75*/
76#define __FPU_USED       0U
77
78#if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_FP
85    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87
88#elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92
93#elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97
98#elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102
103#elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107
108#elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112
113#endif
114
115#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
116
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* __CORE_CM0_H_GENERIC */
123
124#ifndef __CMSIS_GENERIC
125
126#ifndef __CORE_CM0_H_DEPENDANT
127#define __CORE_CM0_H_DEPENDANT
128
129#ifdef __cplusplus
130 extern "C" {
131#endif
132
133/* check device defines and use defaults */
134#if defined __CHECK_DEVICE_DEFINES
135  #ifndef __CM0_REV
136    #define __CM0_REV               0x0000U
137    #warning "__CM0_REV not defined in device header file; using default!"
138  #endif
139
140  #ifndef __NVIC_PRIO_BITS
141    #define __NVIC_PRIO_BITS          2U
142    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
143  #endif
144
145  #ifndef __Vendor_SysTickConfig
146    #define __Vendor_SysTickConfig    0U
147    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
148  #endif
149#endif
150
151/* IO definitions (access restrictions to peripheral registers) */
152/**
153    \defgroup CMSIS_glob_defs CMSIS Global Defines
154
155    <strong>IO Type Qualifiers</strong> are used
156    \li to specify the access to peripheral variables.
157    \li for automatic generation of peripheral register debug information.
158*/
159#ifdef __cplusplus
160  #define   __I     volatile             /*!< Defines 'read only' permissions */
161#else
162  #define   __I     volatile const       /*!< Defines 'read only' permissions */
163#endif
164#define     __O     volatile             /*!< Defines 'write only' permissions */
165#define     __IO    volatile             /*!< Defines 'read / write' permissions */
166
167/* following defines should be used for structure members */
168#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
169#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
170#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
171
172/*@} end of group Cortex_M0 */
173
174
175
176/*******************************************************************************
177 *                 Register Abstraction
178  Core Register contain:
179  - Core Register
180  - Core NVIC Register
181  - Core SCB Register
182  - Core SysTick Register
183 ******************************************************************************/
184/**
185  \defgroup CMSIS_core_register Defines and Type Definitions
186  \brief Type definitions and defines for Cortex-M processor based devices.
187*/
188
189/**
190  \ingroup    CMSIS_core_register
191  \defgroup   CMSIS_CORE  Status and Control Registers
192  \brief      Core Register type definitions.
193  @{
194 */
195
196/**
197  \brief  Union type to access the Application Program Status Register (APSR).
198 */
199typedef union
200{
201  struct
202  {
203    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
204    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
205    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
206    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
207    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
208  } b;                                   /*!< Structure used for bit  access */
209  uint32_t w;                            /*!< Type      used for word access */
210} APSR_Type;
211
212/* APSR Register Definitions */
213#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
214#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
215
216#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
217#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
218
219#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
220#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
221
222#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
223#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
224
225
226/**
227  \brief  Union type to access the Interrupt Program Status Register (IPSR).
228 */
229typedef union
230{
231  struct
232  {
233    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
234    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
235  } b;                                   /*!< Structure used for bit  access */
236  uint32_t w;                            /*!< Type      used for word access */
237} IPSR_Type;
238
239/* IPSR Register Definitions */
240#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
241#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
242
243
244/**
245  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
246 */
247typedef union
248{
249  struct
250  {
251    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
252    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
253    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
254    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
255    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
256    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
257    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
258    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
259  } b;                                   /*!< Structure used for bit  access */
260  uint32_t w;                            /*!< Type      used for word access */
261} xPSR_Type;
262
263/* xPSR Register Definitions */
264#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
265#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
266
267#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
268#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
269
270#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
271#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
272
273#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
274#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
275
276#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
277#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
278
279#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
280#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
281
282
283/**
284  \brief  Union type to access the Control Registers (CONTROL).
285 */
286typedef union
287{
288  struct
289  {
290    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
291    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
292    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
293  } b;                                   /*!< Structure used for bit  access */
294  uint32_t w;                            /*!< Type      used for word access */
295} CONTROL_Type;
296
297/* CONTROL Register Definitions */
298#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
299#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
300
301/*@} end of group CMSIS_CORE */
302
303
304/**
305  \ingroup    CMSIS_core_register
306  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
307  \brief      Type definitions for the NVIC Registers
308  @{
309 */
310
311/**
312  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
313 */
314typedef struct
315{
316  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
317        uint32_t RESERVED0[31U];
318  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
319        uint32_t RESERVED1[31U];
320  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
321        uint32_t RESERVED2[31U];
322  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
323        uint32_t RESERVED3[31U];
324        uint32_t RESERVED4[64U];
325  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
326}  NVIC_Type;
327
328/*@} end of group CMSIS_NVIC */
329
330
331/**
332  \ingroup  CMSIS_core_register
333  \defgroup CMSIS_SCB     System Control Block (SCB)
334  \brief    Type definitions for the System Control Block Registers
335  @{
336 */
337
338/**
339  \brief  Structure type to access the System Control Block (SCB).
340 */
341typedef struct
342{
343  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
344  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
345        uint32_t RESERVED0;
346  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
347  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
348  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
349        uint32_t RESERVED1;
350  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
351  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
352} SCB_Type;
353
354/* SCB CPUID Register Definitions */
355#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
356#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
357
358#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
359#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
360
361#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
362#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
363
364#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
365#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
366
367#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
368#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
369
370/* SCB Interrupt Control State Register Definitions */
371#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
372#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
373
374#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
375#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
376
377#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
378#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
379
380#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
381#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
382
383#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
384#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
385
386#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
387#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
388
389#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
390#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
391
392#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
393#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
394
395#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
396#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
397
398/* SCB Application Interrupt and Reset Control Register Definitions */
399#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
400#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
401
402#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
403#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
405#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
406#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
407
408#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
409#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
410
411#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
412#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
414/* SCB System Control Register Definitions */
415#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
416#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
417
418#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
419#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
420
421#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
422#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
423
424/* SCB Configuration Control Register Definitions */
425#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
426#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
427
428#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
429#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
430
431/* SCB System Handler Control and State Register Definitions */
432#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
433#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
434
435/*@} end of group CMSIS_SCB */
436
437
438/**
439  \ingroup  CMSIS_core_register
440  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
441  \brief    Type definitions for the System Timer Registers.
442  @{
443 */
444
445/**
446  \brief  Structure type to access the System Timer (SysTick).
447 */
448typedef struct
449{
450  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
451  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
452  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
453  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
454} SysTick_Type;
455
456/* SysTick Control / Status Register Definitions */
457#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
458#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
459
460#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
461#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
462
463#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
464#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
465
466#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
467#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
468
469/* SysTick Reload Register Definitions */
470#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
471#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
472
473/* SysTick Current Register Definitions */
474#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
475#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
476
477/* SysTick Calibration Register Definitions */
478#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
479#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
480
481#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
482#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
483
484#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
485#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
486
487/*@} end of group CMSIS_SysTick */
488
489
490/**
491  \ingroup  CMSIS_core_register
492  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
493  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
494            Therefore they are not covered by the Cortex-M0 header file.
495  @{
496 */
497/*@} end of group CMSIS_CoreDebug */
498
499
500/**
501  \ingroup    CMSIS_core_register
502  \defgroup   CMSIS_core_bitfield     Core register bit field macros
503  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
504  @{
505 */
506
507/**
508  \brief   Mask and shift a bit field value for use in a register bit range.
509  \param[in] field  Name of the register bit field.
510  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
511  \return           Masked and shifted value.
512*/
513#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
514
515/**
516  \brief     Mask and shift a register value to extract a bit filed value.
517  \param[in] field  Name of the register bit field.
518  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
519  \return           Masked and shifted bit field value.
520*/
521#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
522
523/*@} end of group CMSIS_core_bitfield */
524
525
526/**
527  \ingroup    CMSIS_core_register
528  \defgroup   CMSIS_core_base     Core Definitions
529  \brief      Definitions for base addresses, unions, and structures.
530  @{
531 */
532
533/* Memory mapping of Core Hardware */
534#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
535#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
536#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
537#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
538
539#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
540#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
541#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
542
543
544/*@} */
545
546
547
548/*******************************************************************************
549 *                Hardware Abstraction Layer
550  Core Function Interface contains:
551  - Core NVIC Functions
552  - Core SysTick Functions
553  - Core Register Access Functions
554 ******************************************************************************/
555/**
556  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
557*/
558
559
560
561/* ##########################   NVIC functions  #################################### */
562/**
563  \ingroup  CMSIS_Core_FunctionInterface
564  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
565  \brief    Functions that manage interrupts and exceptions via the NVIC.
566  @{
567 */
568
569#ifdef CMSIS_NVIC_VIRTUAL
570  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
571    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
572  #endif
573  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
574#else
575  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
576  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
577  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
578  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
579  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
580  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
581  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
582  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
583/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
584  #define NVIC_SetPriority            __NVIC_SetPriority
585  #define NVIC_GetPriority            __NVIC_GetPriority
586  #define NVIC_SystemReset            __NVIC_SystemReset
587#endif /* CMSIS_NVIC_VIRTUAL */
588
589#ifdef CMSIS_VECTAB_VIRTUAL
590  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
591    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
592  #endif
593  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
594#else
595  #define NVIC_SetVector              __NVIC_SetVector
596  #define NVIC_GetVector              __NVIC_GetVector
597#endif  /* (CMSIS_VECTAB_VIRTUAL) */
598
599#define NVIC_USER_IRQ_OFFSET          16
600
601
602/* The following EXC_RETURN values are saved the LR on exception entry */
603#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
604#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
605#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
606
607
608/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
609/* The following MACROS handle generation of the register offset and byte masks */
610#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
611#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
612#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
613
614#define __NVIC_SetPriorityGrouping(X) (void)(X)
615#define __NVIC_GetPriorityGrouping()  (0U)
616
617/**
618  \brief   Enable Interrupt
619  \details Enables a device specific interrupt in the NVIC interrupt controller.
620  \param [in]      IRQn  Device specific interrupt number.
621  \note    IRQn must not be negative.
622 */
623__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
624{
625  if ((int32_t)(IRQn) >= 0)
626  {
627    __COMPILER_BARRIER();
628    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
629    __COMPILER_BARRIER();
630  }
631}
632
633
634/**
635  \brief   Get Interrupt Enable status
636  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
637  \param [in]      IRQn  Device specific interrupt number.
638  \return             0  Interrupt is not enabled.
639  \return             1  Interrupt is enabled.
640  \note    IRQn must not be negative.
641 */
642__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
643{
644  if ((int32_t)(IRQn) >= 0)
645  {
646    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
647  }
648  else
649  {
650    return(0U);
651  }
652}
653
654
655/**
656  \brief   Disable Interrupt
657  \details Disables a device specific interrupt in the NVIC interrupt controller.
658  \param [in]      IRQn  Device specific interrupt number.
659  \note    IRQn must not be negative.
660 */
661__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
662{
663  if ((int32_t)(IRQn) >= 0)
664  {
665    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
666    __DSB();
667    __ISB();
668  }
669}
670
671
672/**
673  \brief   Get Pending Interrupt
674  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
675  \param [in]      IRQn  Device specific interrupt number.
676  \return             0  Interrupt status is not pending.
677  \return             1  Interrupt status is pending.
678  \note    IRQn must not be negative.
679 */
680__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
681{
682  if ((int32_t)(IRQn) >= 0)
683  {
684    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
685  }
686  else
687  {
688    return(0U);
689  }
690}
691
692
693/**
694  \brief   Set Pending Interrupt
695  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
696  \param [in]      IRQn  Device specific interrupt number.
697  \note    IRQn must not be negative.
698 */
699__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
700{
701  if ((int32_t)(IRQn) >= 0)
702  {
703    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
704  }
705}
706
707
708/**
709  \brief   Clear Pending Interrupt
710  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
711  \param [in]      IRQn  Device specific interrupt number.
712  \note    IRQn must not be negative.
713 */
714__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
715{
716  if ((int32_t)(IRQn) >= 0)
717  {
718    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
719  }
720}
721
722
723/**
724  \brief   Set Interrupt Priority
725  \details Sets the priority of a device specific interrupt or a processor exception.
726           The interrupt number can be positive to specify a device specific interrupt,
727           or negative to specify a processor exception.
728  \param [in]      IRQn  Interrupt number.
729  \param [in]  priority  Priority to set.
730  \note    The priority cannot be set for every processor exception.
731 */
732__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
733{
734  if ((int32_t)(IRQn) >= 0)
735  {
736    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
737       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
738  }
739  else
740  {
741    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
742       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
743  }
744}
745
746
747/**
748  \brief   Get Interrupt Priority
749  \details Reads the priority of a device specific interrupt or a processor exception.
750           The interrupt number can be positive to specify a device specific interrupt,
751           or negative to specify a processor exception.
752  \param [in]   IRQn  Interrupt number.
753  \return             Interrupt Priority.
754                      Value is aligned automatically to the implemented priority bits of the microcontroller.
755 */
756__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
757{
758
759  if ((int32_t)(IRQn) >= 0)
760  {
761    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
762  }
763  else
764  {
765    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
766  }
767}
768
769
770/**
771  \brief   Encode Priority
772  \details Encodes the priority for an interrupt with the given priority group,
773           preemptive priority value, and subpriority value.
774           In case of a conflict between priority grouping and available
775           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
776  \param [in]     PriorityGroup  Used priority group.
777  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
778  \param [in]       SubPriority  Subpriority value (starting from 0).
779  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
780 */
781__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
782{
783  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
784  uint32_t PreemptPriorityBits;
785  uint32_t SubPriorityBits;
786
787  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
788  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
789
790  return (
791           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
792           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
793         );
794}
795
796
797/**
798  \brief   Decode Priority
799  \details Decodes an interrupt priority value with a given priority group to
800           preemptive priority value and subpriority value.
801           In case of a conflict between priority grouping and available
802           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
803  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
804  \param [in]     PriorityGroup  Used priority group.
805  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
806  \param [out]     pSubPriority  Subpriority value (starting from 0).
807 */
808__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
809{
810  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
811  uint32_t PreemptPriorityBits;
812  uint32_t SubPriorityBits;
813
814  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
815  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
816
817  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
818  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
819}
820
821
822
823/**
824  \brief   Set Interrupt Vector
825  \details Sets an interrupt vector in SRAM based interrupt vector table.
826           The interrupt number can be positive to specify a device specific interrupt,
827           or negative to specify a processor exception.
828           Address 0 must be mapped to SRAM.
829  \param [in]   IRQn      Interrupt number
830  \param [in]   vector    Address of interrupt handler function
831 */
832__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
833{
834  uint32_t vectors = 0x0U;
835  (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
836  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
837}
838
839
840/**
841  \brief   Get Interrupt Vector
842  \details Reads an interrupt vector from interrupt vector table.
843           The interrupt number can be positive to specify a device specific interrupt,
844           or negative to specify a processor exception.
845  \param [in]   IRQn      Interrupt number.
846  \return                 Address of interrupt handler function
847 */
848__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
849{
850  uint32_t vectors = 0x0U;
851  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
852}
853
854
855/**
856  \brief   System Reset
857  \details Initiates a system reset request to reset the MCU.
858 */
859__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
860{
861  __DSB();                                                          /* Ensure all outstanding memory accesses included
862                                                                       buffered write are completed before reset */
863  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
864                 SCB_AIRCR_SYSRESETREQ_Msk);
865  __DSB();                                                          /* Ensure completion of memory access */
866
867  for(;;)                                                           /* wait until reset */
868  {
869    __NOP();
870  }
871}
872
873/*@} end of CMSIS_Core_NVICFunctions */
874
875
876/* ##########################  FPU functions  #################################### */
877/**
878  \ingroup  CMSIS_Core_FunctionInterface
879  \defgroup CMSIS_Core_FpuFunctions FPU Functions
880  \brief    Function that provides FPU type.
881  @{
882 */
883
884/**
885  \brief   get FPU type
886  \details returns the FPU type
887  \returns
888   - \b  0: No FPU
889   - \b  1: Single precision FPU
890   - \b  2: Double + Single precision FPU
891 */
892__STATIC_INLINE uint32_t SCB_GetFPUType(void)
893{
894    return 0U;           /* No FPU */
895}
896
897
898/*@} end of CMSIS_Core_FpuFunctions */
899
900
901
902/* ##################################    SysTick function  ############################################ */
903/**
904  \ingroup  CMSIS_Core_FunctionInterface
905  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
906  \brief    Functions that configure the System.
907  @{
908 */
909
910#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
911
912/**
913  \brief   System Tick Configuration
914  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
915           Counter is in free running mode to generate periodic interrupts.
916  \param [in]  ticks  Number of ticks between two interrupts.
917  \return          0  Function succeeded.
918  \return          1  Function failed.
919  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
920           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
921           must contain a vendor-specific implementation of this function.
922 */
923__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
924{
925  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
926  {
927    return (1UL);                                                   /* Reload value impossible */
928  }
929
930  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
931  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
932  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
933  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
934                   SysTick_CTRL_TICKINT_Msk   |
935                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
936  return (0UL);                                                     /* Function successful */
937}
938
939#endif
940
941/*@} end of CMSIS_Core_SysTickFunctions */
942
943
944
945
946#ifdef __cplusplus
947}
948#endif
949
950#endif /* __CORE_CM0_H_DEPENDANT */
951
952#endif /* __CMSIS_GENERIC */
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