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stm32g0xx_hal_adc.h

Last change on this file was 6, checked in by f.jahn, 3 months ago

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_hal_adc.h
4	* @author MCD Application Team
5	* @brief Header file of ADC HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.
11	*
12	* This software is licensed under terms that can be found in the LICENSE file
13	* in the root directory of this software component.
14	* If no LICENSE file comes with this software, it is provided AS-IS.
15	*
16	******************************************************************************
17	*/
18
19	/* Define to prevent recursive inclusion -------------------------------------*/
20	#ifndef STM32G0xx_HAL_ADC_H
21	#define STM32G0xx_HAL_ADC_H
22
23	#ifdef __cplusplus
24	extern "C" {
25	#endif
26
27	/* Includes ------------------------------------------------------------------*/
28	#include "stm32g0xx_hal_def.h"
29
30	/* Include low level driver */
31	#include "stm32g0xx_ll_adc.h"
32
33	/** @addtogroup STM32G0xx_HAL_Driver
34	* @{
35	*/
36
37	/** @addtogroup ADC
38	* @{
39	*/
40
41	/* Exported types ------------------------------------------------------------*/
42	/** @defgroup ADC_Exported_Types ADC Exported Types
43	* @{
44	*/
45
46	/**
47	* @brief ADC group regular oversampling structure definition
48	*/
49	typedef struct
50	{
51	uint32_t Ratio; /*!< Configures the oversampling ratio.
52	This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
53
54	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
55	This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
56
57	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
58	This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
59
60	} ADC_OversamplingTypeDef;
61
62	/**
63	* @brief Structure definition of ADC instance and ADC group regular.
64	* @note Parameters of this structure are shared within 2 scopes:
65	* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC
66	* groups regular and injected): ClockPrescaler, Resolution, DataAlign,
67	* ScanConvMode, EOCSelection, LowPowerAutoWait.
68	* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
69	* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
70	* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
71	* ADC state can be either:
72	* - For all parameters: ADC disabled
73	* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on
74	* group regular.
75	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
76	* without error reporting (as it can be the expected behavior in case of intended action to update another
77	* parameter (which fulfills the ADC state condition) on the fly).
78	*/
79	typedef struct
80	{
81	uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
82	clock derived from system clock or PLL (Refer to reference manual for list of
83	clocks available)) and clock prescaler.
84	This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
85	Note: The ADC clock configuration is common to all ADC instances.
86	Note: In case of synchronous clock mode based on HCLK/1, the configuration must
87	be enabled only if the system clock has a 50% duty clock cycle (APB
88	prescaler configured inside RCC must be bypassed and PCLK clock must have
89	50% duty cycle). Refer to reference manual for details.
90	Note: In case of usage of asynchronous clock, the selected clock must be
91	preliminarily enabled at RCC top level.
92	Note: This parameter can be modified only if all ADC instances are disabled. */
93
94	uint32_t Resolution; /*!< Configure the ADC resolution.
95	This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
96
97	uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
98	Refer to reference manual for alignments formats versus resolutions.
99	This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
100
101	uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular.
102	On this STM32 series, ADC group regular sequencer both modes "fully configurable"
103	or "not fully configurable" are available:
104	- sequencer configured to fully configurable:
105	sequencer length and each rank affectation to a channel are configurable.
106	- Sequence length: Set number of ranks in the scan sequence.
107	- Sequence direction: Unless specified in parameters, sequencer
108	scan direction is forward (from rank 1 to rank n).
109	- sequencer configured to not fully configurable:
110	sequencer length and each rank affectation to a channel are fixed by channel
111	HW number.
112	- Sequence length: Number of ranks in the scan sequence is
113	defined by number of channels set in the sequence,
114	rank of each channel is fixed by channel HW number.
115	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
116	- Sequence direction: Unless specified in parameters, sequencer
117	scan direction is forward (from lowest channel number to
118	highest channel number).
119	This parameter can be associated to parameter 'DiscontinuousConvMode' to have
120	main sequence subdivided in successive parts. Sequencer is automatically enabled
121	if several channels are set (sequencer cannot be disabled, as it can be the case
122	on other STM32 devices):
123	If only 1 channel is set: Conversion is performed in single mode.
124	If several channels are set: Conversions are performed in sequence mode.
125	This parameter can be a value of @ref ADC_Scan_mode */
126
127	uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
128	interruption: end of unitary conversion or end of sequence conversions.
129	This parameter can be a value of @ref ADC_EOCSelection. */
130
131	FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
132	previous conversion (for ADC group regular) has been retrieved by user software,
133	using function HAL_ADC_GetValue().
134	This feature automatically adapts the frequency of ADC conversions triggers to
135	the speed of the system that reads the data. Moreover, this avoids risk of
136	overrun for low frequency applications.
137	This parameter can be set to ENABLE or DISABLE.
138	Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
139	HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
140	flag (by CPU to free the IRQ pending event or by DMA).
141	Auto wait will work but fort a very short time, discarding its intended
142	benefit (except specific case of high load of CPU or DMA transfers which
143	can justify usage of auto wait).
144	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
145	when ADC conversion data is needed:
146	use HAL_ADC_PollForConversion() to ensure that conversion is completed and
147	HAL_ADC_GetValue() to retrieve conversion result and trig another
148	conversion start. */
149
150	FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a
151	conversion and automatically wakes-up when a new conversion is triggered
152	(with startup time between trigger and start of sampling).
153	This feature can be combined with automatic wait mode
154	(parameter 'LowPowerAutoWait').
155	This parameter can be set to ENABLE or DISABLE. */
156
157	FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
158	or continuous mode for ADC group regular, after the first ADC conversion
159	start trigger occurred (software start or external trigger). This parameter
160	can be set to ENABLE or DISABLE. */
161
162	uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
163	sequencer.
164	This parameter is dependent on ScanConvMode:
165	- sequencer configured to fully configurable:
166	Number of ranks in the scan sequence is configurable using this parameter.
167	Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
168	parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
169	Afterwards, when all needed sequencer ranks are set, parameter
170	'NbrOfConversion' can be updated without modifying configuration of
171	sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
172	- sequencer configured to not fully configurable:
173	Number of ranks in the scan sequence is defined by number of channels set in
174	the sequence. This parameter is discarded.
175	This parameter must be a number between Min_Data = 1 and Max_Data = 8.
176	Note: This parameter must be modified when no conversion is on going on regular
177	group (ADC disabled, or ADC enabled without continuous mode or external
178	trigger that could launch a conversion). */
179
180	FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
181	in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
182	successive parts).
183	Discontinuous mode is used only if sequencer is enabled (parameter
184	'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
185	Discontinuous mode can be enabled only if continuous mode is disabled.
186	If continuous mode is enabled, this parameter setting is discarded.
187	This parameter can be set to ENABLE or DISABLE.
188	Note: On this STM32 series, ADC group regular number of discontinuous
189	ranks increment is fixed to one-by-one. */
190
191	uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
192	start.
193	If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
194	is used instead.
195	This parameter can be a value of @ref ADC_regular_external_trigger_source.
196	Caution: external trigger source is common to all ADC instances. */
197
198	uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
199	If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
200	This parameter can be a value of @ref ADC_regular_external_trigger_edge */
201
202	FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
203	transfer stops when number of conversions is reached) or in continuous
204	mode (DMA transfer unlimited, whatever number of conversions).
205	This parameter can be set to ENABLE or DISABLE.
206	Note: In continuous mode, DMA must be configured in circular mode.
207	Otherwise an overrun will be triggered when DMA buffer maximum
208	pointer is reached. */
209
210	uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
211	This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
212	Note: In case of overrun set to data preserved and usage with programming model
213	with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
214	conversion flags, this induces the release of the preserved data. If
215	needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
216	placed in user program code (called before end of conversion flags clear)
217	Note: Error reporting with respect to the conversion mode:
218	- Usage with ADC conversion by polling for event or interruption: Error is
219	reported only if overrun is set to data preserved. If overrun is set to
220	data overwritten, user can willingly not read all the converted data,
221	this is not considered as an erroneous case.
222	- Usage with ADC conversion by DMA: Error is reported whatever overrun
223	setting (DMA is expected to process all data from data register). */
224
225	uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
226	Unit: ADC clock cycles
227	Conversion time is the addition of sampling time and processing time
228	(12.5 ADC clock cycles at ADC resolution 12 bits,
229	10.5 cycles at 10 bits,
230	8.5 cycles at 8 bits,
231	6.5 cycles at 6 bits).
232	Note: On this STM32 family, two different sampling time settings are available,
233	each channel can use one of these two settings. On some other STM32 devices
234	this parameter in channel wise and is located into ADC channel
235	initialization structure.
236	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
237	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
238	sampling time constraints must be respected (sampling time can be adjusted
239	in function of ADC clock frequency and sampling time setting)
240	Refer to device datasheet for timings values, parameters TS_vrefint,
241	TS_vbat, TS_temp (values rough order: few tens of microseconds). */
242
243	uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
244	Unit: ADC clock cycles
245	Conversion time is the addition of sampling time and processing time
246	(12.5 ADC clock cycles at ADC resolution 12 bits,
247	10.5 cycles at 10 bits,
248	8.5 cycles at 8 bits,
249	6.5 cycles at 6 bits).
250	Note: On this STM32 family, two different sampling time settings are available,
251	each channel can use one of these two settings. On some other STM32 devices
252	this parameter in channel wise and is located into ADC channel
253	initialization structure.
254	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
255	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
256	sampling time constraints must be respected (sampling time can be adjusted
257	in function of ADC clock frequency and sampling time setting)
258	Refer to device datasheet for timings values, parameters TS_vrefint,
259	TS_vbat, TS_temp (values rough order: few tens of microseconds). */
260
261	FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
262	This parameter can be set to ENABLE or DISABLE.
263	Note: This parameter can be modified only if there is no conversion is
264	ongoing on ADC group regular. */
265
266	ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
267	Caution: this setting overwrites the previous oversampling configuration
268	if oversampling is already enabled. */
269
270	uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
271	This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
272	Note: ADC trigger frequency mode must be set to low frequency when
273	a duration is exceeded before ADC conversion start trigger event
274	(between ADC enable and ADC conversion start trigger event
275	or between two ADC conversion start trigger event).
276	Duration value: Refer to device datasheet, parameter "tIdle".
277	Note: When ADC trigger frequency mode is set to low frequency,
278	some rearm cycles are inserted before performing ADC conversion
279	start, inducing a delay of 2 ADC clock cycles. */
280
281	} ADC_InitTypeDef;
282
283	/**
284	* @brief Structure definition of ADC channel for regular group
285	* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
286	* ADC state can be either:
287	* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
288	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
289	* without error reporting (as it can be the expected behavior in case of intended action to update another
290	* parameter (which fulfills the ADC state condition) on the fly).
291	*/
292	typedef struct
293	{
294	uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
295	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
296	Note: Depending on devices and ADC instances, some channels may not be available
297	on device package pins. Refer to device datasheet for channels
298	availability. */
299
300	uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its
301	conversion rank.
302	This parameter is dependent on ScanConvMode:
303	- sequencer configured to fully configurable:
304	Channels ordering into each rank of scan sequence:
305	whatever channel can be placed into whatever rank.
306	- sequencer configured to not fully configurable:
307	rank of each channel is fixed by channel HW number.
308	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
309	Despite the channel rank is fixed, this parameter allow an additional
310	possibility: to remove the selected rank (selected channel) from sequencer.
311	This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
312
313	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
314	Unit: ADC clock cycles
315	Conversion time is the addition of sampling time and processing time
316	(12.5 ADC clock cycles at ADC resolution 12 bits,
317	10.5 cycles at 10 bits,
318	8.5 cycles at 8 bits,
319	6.5 cycles at 6 bits).
320	This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
321	Note: On this STM32 family, two different sampling time settings are available
322	(refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
323	each channel can use one of these two settings.
324
325	Note: In case of usage of internal measurement channels (VrefInt/Vbat/
326	TempSensor), sampling time constraints must be respected (sampling time
327	can be adjusted in function of ADC clock frequency and sampling time
328	setting)
329	Refer to device datasheet for timings values. */
330
331	} ADC_ChannelConfTypeDef;
332
333	/**
334	* @brief Structure definition of ADC analog watchdog
335	* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
336	* ADC state can be either:
337	* - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
338	on going on ADC groups regular.
339	* - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
340	*/
341	typedef struct
342	{
343	uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
344	For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
345	by setting parameter 'WatchdogMode')
346	For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
347	of 'HAL_ADC_AnalogWDGConfig()' for each channel)
348	This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
349
350	uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
351	For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
352	channels, ADC group regular.
353	For Analog Watchdog 2 and 3: Several channels can be monitored by applying
354	successively the AWD init structure.
355	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
356
357	uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
358	For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
359	is configured on single channel (only 1 channel can be
360	monitored).
361	For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
362	call successively the function HAL_ADC_AnalogWDGConfig()
363	for each channel to be added (or removed with value
364	'ADC_ANALOGWATCHDOG_NONE').
365	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
366
367	FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
368	This parameter can be set to ENABLE or DISABLE */
369
370	uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
371	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
372	number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
373	respectively.
374	Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
375	resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
376	LSB are ignored.
377	Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
378	impacted: the comparison of analog watchdog thresholds is done on
379	oversampling final computation (after ratio and shift application):
380	ADC data register bitfield [15:4] (12 most significant bits). */
381
382	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
383	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
384	number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
385	respectively.
386	Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
387	resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
388	LSB are ignored.
389	Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
390	impacted: the comparison of analog watchdog thresholds is done on
391	oversampling final computation (after ratio and shift application):
392	ADC data register bitfield [15:4] (12 most significant bits).*/
393	} ADC_AnalogWDGConfTypeDef;
394
395	/** @defgroup ADC_States ADC States
396	* @{
397	*/
398
399	/**
400	* @brief HAL ADC state machine: ADC states definition (bitfields)
401	* @note ADC state machine is managed by bitfields, state must be compared
402	* with bit by bit.
403	* For example:
404	* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
405	* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
406	*/
407	/* States of ADC global scope */
408	#define HAL_ADC_STATE_RESET (0x00000000UL) /!< ADC not yet initialized or disabled /
409	#define HAL_ADC_STATE_READY (0x00000001UL) /!< ADC peripheral ready for use /
410	#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /!< ADC is busy from internal process (ex : calibration, ...) /
411	#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /!< TimeOut occurrence /
412
413	/* States of ADC errors */
414	#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /!< Internal error occurrence /
415	#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /!< Configuration error occurrence /
416	#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /!< DMA error occurrence /
417
418	/* States of ADC group regular */
419	#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
420	(either by continuous mode, external trigger, low power
421	auto power-on (if feature available), multimode ADC master
422	control (if feature available)) */
423	#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /!< Conversion data available on group regular /
424	#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /!< Overrun occurrence /
425	#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
426	raised */
427
428	/* States of ADC group injected */
429	#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group
430	injected is ongoing or can occur (either by auto-injection
431	mode, external trigger, low power auto power-on (if feature
432	available), multimode ADC master control (if feature
433	available))*/
434	#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data
435	available on group injected */
436	#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow
437	occurrence */
438
439	/* States of ADC analog watchdogs */
440	#define HAL_ADC_STATE_AWD1 (0x00010000UL) /!< Out-of-window occurrence of ADC analog watchdog 1 /
441	#define HAL_ADC_STATE_AWD2 (0x00020000UL) /!< Out-of-window occurrence of ADC analog watchdog 2 /
442	#define HAL_ADC_STATE_AWD3 (0x00040000UL) /!< Out-of-window occurrence of ADC analog watchdog 3 /
443
444	/* States of ADC multi-mode */
445	#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave
446	state, controlled by another ADC master (when feature
447	available) */
448
449
450	/**
451	* @}
452	*/
453
454	/**
455	* @brief ADC handle Structure definition
456	*/
457	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
458	typedef struct __ADC_HandleTypeDef
459	#else
460	typedef struct
461	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
462	{
463	ADC_TypeDef Instance; /!< Register base address */
464	ADC_InitTypeDef Init; /!< ADC initialization parameters and regular conversions setting /
465	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
466	HAL_LockTypeDef Lock; /!< ADC locking object /
467	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
468	__IO uint32_t ErrorCode; /!< ADC Error code /
469
470	uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks
471	setting, used in mode "fully configurable" (refer to
472	parameter 'ScanConvMode') */
473	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
474	void (* ConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion complete callback */
475	void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion DMA half-transfer
476	callback */
477	void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 1 callback */
478	void (* ErrorCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC error callback */
479	void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 2 callback */
480	void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 3 callback */
481	void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC end of sampling callback */
482	void (* MspInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp Init callback */
483	void (* MspDeInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp DeInit callback */
484	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
485	} ADC_HandleTypeDef;
486
487	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
488	/**
489	* @brief HAL ADC Callback ID enumeration definition
490	*/
491	typedef enum
492	{
493	HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /!< ADC conversion complete callback ID /
494	HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /!< ADC conversion DMA half-transfer callback ID /
495	HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /!< ADC analog watchdog 1 callback ID /
496	HAL_ADC_ERROR_CB_ID = 0x03U, /!< ADC error callback ID /
497	HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /!< ADC analog watchdog 2 callback ID /
498	HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /!< ADC analog watchdog 3 callback ID /
499	HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /!< ADC end of sampling callback ID /
500	HAL_ADC_MSPINIT_CB_ID = 0x09U, /!< ADC Msp Init callback ID /
501	HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /!< ADC Msp DeInit callback ID /
502	} HAL_ADC_CallbackIDTypeDef;
503
504	/**
505	* @brief HAL ADC Callback pointer definition
506	*/
507	typedef void (pADC_CallbackTypeDef)(ADC_HandleTypeDef hadc); /!< pointer to a ADC callback function /
508
509	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
510
511	/**
512	* @}
513	*/
514
515
516	/* Exported constants --------------------------------------------------------*/
517
518	/** @defgroup ADC_Exported_Constants ADC Exported Constants
519	* @{
520	*/
521
522	/** @defgroup ADC_Error_Code ADC Error Code
523	* @{
524	*/
525	#define HAL_ADC_ERROR_NONE (0x00U) /!< No error /
526	#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
527	enable/disable, erroneous state, ...) */
528	#define HAL_ADC_ERROR_OVR (0x02U) /!< Overrun error /
529	#define HAL_ADC_ERROR_DMA (0x04U) /!< DMA transfer error /
530	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
531	#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /!< Invalid Callback error /
532	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
533	/**
534	* @}
535	*/
536
537	/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
538	* @{
539	*/
540	#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
541	without prescaler. This configuration must be enabled only if PCLK has
542	a 50% duty clock cycle (APB prescaler configured inside the RCC must
543	be bypassed and the system clock must by 50% duty cycle) */
544	#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
545	with prescaler division by 2 */
546	#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
547	with prescaler division by 4 */
548
549	#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
550	prescaler */
551	#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
552	division by 2 */
553	#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
554	division by 4 */
555	#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
556	division by 6 */
557	#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
558	division by 8 */
559	#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
560	division by 10 */
561	#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
562	division by 12 */
563	#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
564	division by 16 */
565	#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
566	division by 32 */
567	#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
568	division by 64 */
569	#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
570	division by 128 */
571	#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
572	division by 256 */
573	/**
574	* @}
575	*/
576
577	/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
578	* @{
579	*/
580	#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /!< ADC resolution 12 bits /
581	#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /!< ADC resolution 10 bits /
582	#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /!< ADC resolution 8 bits /
583	#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /!< ADC resolution 6 bits /
584	/**
585	* @}
586	*/
587
588	/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
589	* @{
590	*/
591	#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
592	(alignment on data register LSB bit 0)*/
593	#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
594	(alignment on data register MSB bit 15)*/
595	/**
596	* @}
597	*/
598
599	/** @defgroup ADC_Scan_mode ADC sequencer scan mode
600	* @{
601	*/
602	/* Note: On this STM32 family, ADC group regular sequencer both modes */
603	/* "fully configurable" or "not fully configurable" are */
604	/* available. */
605	/* Scan mode values must be compatible with other STM32 devices having */
606	/* a configurable sequencer. */
607	/* Scan direction setting values are defined by taking in account */
608	/* already defined values for other STM32 devices: */
609	/* ADC_SCAN_DISABLE (0x00000000UL) */
610	/* ADC_SCAN_ENABLE (0x00000001UL) */
611	/* Sequencer fully configurable with only rank 1 enabled is considered */
612	/* as default setting equivalent to scan enable. */
613	/* In case of migration from another STM32 device, the user will be */
614	/* warned of change of setting choices with assert check. */
615	/* Sequencer set to fully configurable */
616	#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable:
617	only the rank 1 is enabled (no scan sequence on several ranks) */
618	#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable:
619	sequencer length and each rank affectation to a channel are configurable. */
620
621	/* Sequencer set to not fully configurable */
622	#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable:
623	sequencer length and each rank affectation to a channel are fixed by
624	channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
625	Scan direction forward: from channel 0 to channel 18 */
626	#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \
627	\| ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable:
628	sequencer length and each rank affectation to a channel are fixed by
629	channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
630	Scan direction backward: from channel 18 to channel 0 */
631
632	#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */
633	#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */
634	/**
635	* @}
636	*/
637
638	/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
639	* @{
640	*/
641	/* ADC group regular trigger sources for all ADC instances */
642	#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion
643	trigger software start */
644	#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
645	trigger from external peripheral: TIM1 TRGO. */
646	#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion
647	trigger from external peripheral: TIM1 channel 4 event (capture compare). */
648	#if defined(TIM2)
649	#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
650	trigger from external peripheral: TIM2 TRGO. */
651	#endif /* TIM2 */
652	#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
653	trigger from external peripheral: TIM3 TRGO. */
654	#if defined(TIM4)
655	#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
656	trigger from external peripheral: TIM4 TRGO. */
657	#endif /* TIM4 */
658	#if defined(TIM6)
659	#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
660	trigger from external peripheral: TIM6 TRGO. */
661	#endif /* TIM6 */
662	#if defined(TIM15)
663	#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
664	trigger from external peripheral: TIM15 TRGO. */
665	#endif /* TIM15 */
666	#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion
667	trigger from external peripheral: external interrupt line 11. */
668	/**
669	* @}
670	*/
671
672	/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
673	* @{
674	*/
675	#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
676	disabled (SW start)*/
677	#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion
678	trigger polarity set to rising edge */
679	#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion
680	trigger polarity set to falling edge */
681	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
682	trigger polarity set to both rising and falling edges */
683	/**
684	* @}
685	*/
686
687	/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
688	* @{
689	*/
690	#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /!< End of unitary conversion flag /
691	#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /!< End of sequence conversions flag /
692	/**
693	* @}
694	*/
695
696	/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
697	* @{
698	*/
699	#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case
700	of overrun: data preserved */
701	#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case
702	of overrun: data overwritten */
703	/**
704	* @}
705	*/
706
707	/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
708	* @{
709	*/
710	#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of
711	ranks in the sequence is defined by number of channels enabled, rank of
712	each channel is defined by channel number (channel 0 fixed on rank 0,
713	channel 1 fixed on rank1, ...).
714	Setting relevant if parameter "ScanConvMode" is set to sequencer not fully
715	configurable. */
716	#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from
717	sequencer.
718	Setting relevant if parameter "ScanConvMode" is set to sequencer not fully
719	configurable. */
720
721	#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /!< ADC group regular sequencer rank 1 /
722	#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /!< ADC group regular sequencer rank 2 /
723	#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /!< ADC group regular sequencer rank 3 /
724	#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /!< ADC group regular sequencer rank 4 /
725	#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /!< ADC group regular sequencer rank 5 /
726	#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /!< ADC group regular sequencer rank 6 /
727	#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /!< ADC group regular sequencer rank 7 /
728	#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /!< ADC group regular sequencer rank 8 /
729	/**
730	* @}
731	*/
732
733	/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
734	* @{
735	*/
736	#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of
737	channels: sampling time nb 1 */
738	#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of
739	channels: sampling time nb 2 */
740	/**
741	* @}
742	*/
743
744	/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
745	* @{
746	*/
747	#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /!< Sampling time 1.5 ADC clock cycle /
748	#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /!< Sampling time 3.5 ADC clock cycles /
749	#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /!< Sampling time 7.5 ADC clock cycles /
750	#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /!< Sampling time 12.5 ADC clock cycles /
751	#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /!< Sampling time 19.5 ADC clock cycles /
752	#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /!< Sampling time 39.5 ADC clock cycles /
753	#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /!< Sampling time 79.5 ADC clock cycles /
754	#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /!< Sampling time 160.5 ADC clock cycles /
755	/**
756	* @}
757	*/
758
759	/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
760	* @{
761	*/
762	#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /!< External channel (GPIO pin) ADCx_IN0 /
763	#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /!< External channel (GPIO pin) ADCx_IN1 /
764	#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /!< External channel (GPIO pin) ADCx_IN2 /
765	#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /!< External channel (GPIO pin) ADCx_IN3 /
766	#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /!< External channel (GPIO pin) ADCx_IN4 /
767	#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /!< External channel (GPIO pin) ADCx_IN5 /
768	#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /!< External channel (GPIO pin) ADCx_IN6 /
769	#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /!< External channel (GPIO pin) ADCx_IN7 /
770	#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /!< External channel (GPIO pin) ADCx_IN8 /
771	#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /!< External channel (GPIO pin) ADCx_IN9 /
772	#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /!< External channel (GPIO pin) ADCx_IN10 /
773	#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /!< External channel (GPIO pin) ADCx_IN11 /
774	#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /!< External channel (GPIO pin) ADCx_IN12 /
775	#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /!< External channel (GPIO pin) ADCx_IN13 /
776	#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /!< External channel (GPIO pin) ADCx_IN14 /
777	#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /!< External channel (GPIO pin) ADCx_IN15 /
778	#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /!< External channel (GPIO pin) ADCx_IN16 /
779	#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /!< External channel (GPIO pin) ADCx_IN17 /
780	#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /!< External channel (GPIO pin) ADCx_IN18 /
781	#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal
782	voltage reference. */
783	#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /!< Internal channel Temperature sensor. /
784	#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage
785	through a divider ladder of factor 1/3 to have channel voltage always below
786	Vdda. */
787	/**
788	* @}
789	*/
790
791	/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
792	* @{
793	*/
794	#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /!< ADC analog watchdog number 1 /
795	#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /!< ADC analog watchdog number 2 /
796	#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /!< ADC analog watchdog number 3 /
797	/**
798	* @}
799	*/
800
801	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
802	* @{
803	*/
804	#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /!< ADC AWD not selected /
805	#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL \| ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular
806	group single channel */
807	#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular
808	group all channels */
809	/**
810	* @}
811	*/
812
813	/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
814	* @{
815	*/
816	/**
817	* @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
818	* to result as the ADC oversampling conversion data (before potential shift)
819	*/
820	#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /!< ADC oversampling ratio 2 /
821	#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /!< ADC oversampling ratio 4 /
822	#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /!< ADC oversampling ratio 8 /
823	#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /!< ADC oversampling ratio 16 /
824	#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /!< ADC oversampling ratio 32 /
825	#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /!< ADC oversampling ratio 64 /
826	#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /!< ADC oversampling ratio 128 /
827	#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /!< ADC oversampling ratio 256 /
828	/**
829	* @}
830	*/
831
832	/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
833	* @{
834	*/
835	/**
836	* @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
837	* conversion data)
838	*/
839	#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /!< ADC oversampling no shift /
840	#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /!< ADC oversampling right shift of 1 ranks /
841	#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /!< ADC oversampling right shift of 2 ranks /
842	#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /!< ADC oversampling right shift of 3 ranks /
843	#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /!< ADC oversampling right shift of 4 ranks /
844	#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /!< ADC oversampling right shift of 5 ranks /
845	#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /!< ADC oversampling right shift of 6 ranks /
846	#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /!< ADC oversampling right shift of 7 ranks /
847	#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /!< ADC oversampling right shift of 8 ranks /
848	/**
849	* @}
850	*/
851
852	/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
853	* @{
854	*/
855	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
856	continuous mode (all conversions of OVS ratio are done from 1 trigger) */
857	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
858	discontinuous mode (each conversion of OVS ratio needs a trigger) */
859	/**
860	* @}
861	*/
862
863	/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
864	* @{
865	*/
866
867	/**
868	* @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
869	* start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion
870	* start trigger event).
871	* Duration value: Refer to device datasheet, parameter "tIdle".
872	*/
873	#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /!< Trigger frequency mode set to high frequency. /
874	#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /!< Trigger frequency mode set to low frequency. /
875	/**
876	* @}
877	*/
878
879	/** @defgroup ADC_Event_type ADC Event type
880	* @{
881	*/
882	/**
883	* @note Analog watchdog 1 is available on all stm32 series
884	* Analog watchdog 2 and 3 are not available on all series
885	*/
886	#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /!< ADC End of Sampling event /
887	#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /!< ADC Analog watchdog 1 event (main analog watchdog) /
888	#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /!< ADC Analog watchdog 2 event (additional analog watchdog) /
889	#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /!< ADC Analog watchdog 3 event (additional analog watchdog) /
890	#define ADC_OVR_EVENT (ADC_FLAG_OVR) /!< ADC overrun event /
891	/**
892	* @}
893	*/
894	#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
895	with other STM32 devices having only one analog watchdog */
896
897	/** @defgroup ADC_interrupts_definition ADC interrupts definition
898	* @{
899	*/
900	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready interrupt source /
901	#define ADC_IT_CCRDY ADC_IER_CCRDYIE /!< ADC channel configuration ready interrupt source /
902	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of sampling interrupt source /
903	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of regular conversion interrupt source /
904	#define ADC_IT_EOS ADC_IER_EOSIE /!< ADC End of regular sequence of conversions interrupt source /
905	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
906	#define ADC_IT_AWD1 ADC_IER_AWD1IE /!< ADC Analog watchdog 1 interrupt source (main analog watchdog) /
907	#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog
908	watchdog) */
909	#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog
910	watchdog) */
911	/**
912	* @}
913	*/
914
915	/** @defgroup ADC_flags_definition ADC flags definition
916	* @{
917	*/
918	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready flag /
919	#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /!< ADC channel configuration ready flag /
920	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
921	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
922	#define ADC_FLAG_EOS ADC_ISR_EOS /!< ADC End of Regular sequence of Conversions flag /
923	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
924	#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /!< ADC Analog watchdog 1 flag (main analog watchdog) /
925	#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /!< ADC Analog watchdog 2 flag (additional analog watchdog) /
926	#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /!< ADC Analog watchdog 3 flag (additional analog watchdog) /
927	/**
928	* @}
929	*/
930
931	/**
932	* @}
933	*/
934
935	/* Private macro -------------------------------------------------------------*/
936
937	/** @defgroup ADC_Private_Macros ADC Private Macros
938	* @{
939	*/
940	/* Macro reserved for internal HAL driver usage, not intended to be used in */
941	/* code of final user. */
942
943	/**
944	* @brief Test if conversion trigger of regular group is software start
945	* or external trigger.
946	* @param __HANDLE__ ADC handle
947	* @retval SET (software start) or RESET (external trigger)
948	*/
949	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
950	(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
951
952	/**
953	* @brief Return resolution bits in CFGR1 register RES[1:0] field.
954	* @param __HANDLE__ ADC handle
955	* @retval Value of bitfield RES in CFGR1 register.
956	*/
957	#define ADC_GET_RESOLUTION(__HANDLE__) \
958	(LL_ADC_GetResolution((__HANDLE__)->Instance))
959
960	/**
961	* @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
962	* @param __HANDLE__ ADC handle
963	* @retval None
964	*/
965	#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
966
967	/**
968	* @brief Simultaneously clear and set specific bits of the handle State.
969	* @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
970	* the first parameter is the ADC handle State, the second parameter is the
971	* bit field to clear, the third and last parameter is the bit field to set.
972	* @retval None
973	*/
974	#define ADC_STATE_CLR_SET MODIFY_REG
975
976	/**
977	* @brief Enable ADC discontinuous conversion mode for regular group
978	* @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
979	* @retval None
980	*/
981	#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
982	((_REG_DISCONTINUOUS_MODE_) << 16U)
983
984	/**
985	* @brief Enable the ADC auto off mode.
986	* @param _AUTOOFF_ Auto off bit enable or disable.
987	* @retval None
988	*/
989	#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
990	((_AUTOOFF_) << 15U)
991
992	/**
993	* @brief Enable the ADC auto delay mode.
994	* @param _AUTOWAIT_ Auto delay bit enable or disable.
995	* @retval None
996	*/
997	#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
998	((_AUTOWAIT_) << 14U)
999
1000	/**
1001	* @brief Enable ADC continuous conversion mode.
1002	* @param _CONTINUOUS_MODE_ Continuous mode.
1003	* @retval None
1004	*/
1005	#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
1006	((_CONTINUOUS_MODE_) << 13U)
1007
1008	/**
1009	* @brief Enable ADC overrun mode.
1010	* @param _OVERRUN_MODE_ Overrun mode.
1011	* @retval Overrun bit setting to be programmed into CFGR register
1012	*/
1013	/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
1014	/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
1015	/* as the default case to be compliant with other STM32 devices. */
1016	#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
1017	( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
1018	)? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
1019	)
1020
1021	/**
1022	* @brief Set ADC scan mode with differentiation of sequencer setting
1023	* fixed or configurable
1024	* @param _SCAN_MODE_ Scan conversion mode.
1025	* @retval None
1026	*/
1027	/* Note: Scan mode set using this macro (instead of parameter direct set) */
1028	/* due to different modes on other STM32 devices: */
1029	/* if scan mode is disabled, sequencer is set to fully configurable */
1030	/* with setting of only rank 1 enabled afterwards. */
1031	#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
1032	( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \
1033	)? \
1034	((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \
1035	: \
1036	(ADC_CFGR1_CHSELRMOD) \
1037	)
1038
1039	/**
1040	* @brief Enable the ADC DMA continuous request.
1041	* @param _DMACONTREQ_MODE_: DMA continuous request mode.
1042	* @retval None
1043	*/
1044	#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
1045	((_DMACONTREQ_MODE_) << 1U)
1046
1047	/**
1048	* @brief Shift the AWD threshold in function of the selected ADC resolution.
1049	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
1050	* If resolution 12 bits, no shift.
1051	* If resolution 10 bits, shift of 2 ranks on the left.
1052	* If resolution 8 bits, shift of 4 ranks on the left.
1053	* If resolution 6 bits, shift of 6 ranks on the left.
1054	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
1055	* @param __HANDLE__ ADC handle
1056	* @param _Threshold_ Value to be shifted
1057	* @retval None
1058	*/
1059	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
1060	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
1061
1062	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
1063	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
1064	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
1065	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
1066	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
1067	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
1068	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
1069	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
1070	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
1071	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
1072	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
1073	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
1074	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
1075	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
1076	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
1077
1078	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
1079	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
1080	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
1081	((RESOLUTION) == ADC_RESOLUTION_6B) )
1082
1083	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
1084	((ALIGN) == ADC_DATAALIGN_LEFT) )
1085
1086	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
1087	((SCAN_MODE) == ADC_SCAN_ENABLE) \|\| \
1088	((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) \|\| \
1089	((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) )
1090
1091	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
1092	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
1093	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
1094	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
1095
1096	#if defined(TIM15) && defined(TIM6) && defined(TIM2)
1097	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) \|\| \
1098	((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) \|\| \
1099	((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) \|\| \
1100	((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) \|\| \
1101	((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) \|\| \
1102	((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) \|\| \
1103	((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) \|\| \
1104	((REGTRIG) == ADC_SOFTWARE_START) )
1105	#elif defined(TIM15) && defined(TIM6)
1106	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) \|\| \
1107	((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) \|\| \
1108	((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) \|\| \
1109	((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) \|\| \
1110	((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) \|\| \
1111	((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) \|\| \
1112	((REGTRIG) == ADC_SOFTWARE_START) )
1113	#elif defined(TIM2)
1114	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) \|\| \
1115	((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) \|\| \
1116	((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) \|\| \
1117	((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) \|\| \
1118	((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) \|\| \
1119	((REGTRIG) == ADC_SOFTWARE_START) )
1120	#else
1121	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) \|\| \
1122	((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) \|\| \
1123	((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) \|\| \
1124	((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) \|\| \
1125	((REGTRIG) == ADC_SOFTWARE_START) )
1126	#endif /* TIM15 && TIM6 && TIM2 */
1127
1128	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
1129	((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
1130
1131	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
1132	((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
1133
1134	#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) \|\| \
1135	((RANK) == ADC_RANK_NONE) )
1136
1137	#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) \|\| \
1138	((RANK) == ADC_REGULAR_RANK_2 ) \|\| \
1139	((RANK) == ADC_REGULAR_RANK_3 ) \|\| \
1140	((RANK) == ADC_REGULAR_RANK_4 ) \|\| \
1141	((RANK) == ADC_REGULAR_RANK_5 ) \|\| \
1142	((RANK) == ADC_REGULAR_RANK_6 ) \|\| \
1143	((RANK) == ADC_REGULAR_RANK_7 ) \|\| \
1144	((RANK) == ADC_REGULAR_RANK_8 ) )
1145
1146	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
1147	((CHANNEL) == ADC_CHANNEL_1) \|\| \
1148	((CHANNEL) == ADC_CHANNEL_2) \|\| \
1149	((CHANNEL) == ADC_CHANNEL_3) \|\| \
1150	((CHANNEL) == ADC_CHANNEL_4) \|\| \
1151	((CHANNEL) == ADC_CHANNEL_5) \|\| \
1152	((CHANNEL) == ADC_CHANNEL_6) \|\| \
1153	((CHANNEL) == ADC_CHANNEL_7) \|\| \
1154	((CHANNEL) == ADC_CHANNEL_8) \|\| \
1155	((CHANNEL) == ADC_CHANNEL_9) \|\| \
1156	((CHANNEL) == ADC_CHANNEL_10) \|\| \
1157	((CHANNEL) == ADC_CHANNEL_11) \|\| \
1158	((CHANNEL) == ADC_CHANNEL_12) \|\| \
1159	((CHANNEL) == ADC_CHANNEL_13) \|\| \
1160	((CHANNEL) == ADC_CHANNEL_14) \|\| \
1161	((CHANNEL) == ADC_CHANNEL_15) \|\| \
1162	((CHANNEL) == ADC_CHANNEL_16) \|\| \
1163	((CHANNEL) == ADC_CHANNEL_17) \|\| \
1164	((CHANNEL) == ADC_CHANNEL_18) \|\| \
1165	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
1166	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
1167	((CHANNEL) == ADC_CHANNEL_VBAT) )
1168
1169	#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) \|\| \
1170	((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) )
1171
1172	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
1173	((TIME) == ADC_SAMPLETIME_3CYCLES_5) \|\| \
1174	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
1175	((TIME) == ADC_SAMPLETIME_12CYCLES_5) \|\| \
1176	((TIME) == ADC_SAMPLETIME_19CYCLES_5) \|\| \
1177	((TIME) == ADC_SAMPLETIME_39CYCLES_5) \|\| \
1178	((TIME) == ADC_SAMPLETIME_79CYCLES_5) \|\| \
1179	((TIME) == ADC_SAMPLETIME_160CYCLES_5) )
1180
1181	#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) \|\| \
1182	((WATCHDOG) == ADC_ANALOGWATCHDOG_2) \|\| \
1183	((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
1184
1185	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
1186	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
1187	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
1188
1189	#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) \|\| \
1190	((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
1191
1192	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) \|\| \
1193	((EVENT) == ADC_AWD1_EVENT) \|\| \
1194	((EVENT) == ADC_AWD2_EVENT) \|\| \
1195	((EVENT) == ADC_AWD3_EVENT) \|\| \
1196	((EVENT) == ADC_OVR_EVENT) )
1197
1198	/**
1199	* @brief Verify that a given value is aligned with the ADC resolution range.
1200	* @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
1201	* @param __ADC_VALUE__ value checked against the resolution.
1202	* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
1203	*/
1204	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
1205	((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
1206
1207	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
1208	* @{
1209	*/
1210	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
1211	/**
1212	* @}
1213	*/
1214
1215
1216	/* Private constants ---------------------------------------------------------*/
1217
1218	/** @defgroup ADC_Private_Constants ADC Private Constants
1219	* @{
1220	*/
1221
1222	/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
1223	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD \| ADC_FLAG_OVR \| ADC_FLAG_EOS \| ADC_FLAG_EOC)
1224
1225	/* Internal definition to differentiate sequencer setting fixed or configurable */
1226	#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U
1227
1228	/**
1229	* @}
1230	*/
1231
1232	/* Exported macro ------------------------------------------------------------*/
1233
1234	/** @defgroup ADC_Exported_Macros ADC Exported Macros
1235	* @{
1236	*/
1237	/* Macro for internal HAL driver usage, and possibly can be used into code of */
1238	/* final user. */
1239
1240	/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
1241	* @{
1242	*/
1243
1244	/** @brief Reset ADC handle state.
1245	* @param __HANDLE__ ADC handle
1246	* @retval None
1247	*/
1248	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1249	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1250	do{ \
1251	(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
1252	(__HANDLE__)->MspInitCallback = NULL; \
1253	(__HANDLE__)->MspDeInitCallback = NULL; \
1254	} while(0)
1255	#else
1256	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1257	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
1258	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1259
1260	/**
1261	* @brief Enable ADC interrupt.
1262	* @param __HANDLE__ ADC handle
1263	* @param __INTERRUPT__ ADC Interrupt
1264	* This parameter can be one of the following values:
1265	* @arg @ref ADC_IT_RDY ADC Ready interrupt source
1266	* @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
1267	* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1268	* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1269	* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1270	* @arg @ref ADC_IT_OVR ADC overrun interrupt source
1271	* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1272	* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1273	* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1274	* @retval None
1275	*/
1276	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1277	(((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
1278
1279	/**
1280	* @brief Disable ADC interrupt.
1281	* @param __HANDLE__ ADC handle
1282	* @param __INTERRUPT__ ADC Interrupt
1283	* This parameter can be one of the following values:
1284	* @arg @ref ADC_IT_RDY ADC Ready interrupt source
1285	* @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
1286	* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1287	* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1288	* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1289	* @arg @ref ADC_IT_OVR ADC overrun interrupt source
1290	* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1291	* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1292	* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1293	* @retval None
1294	*/
1295	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1296	(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
1297
1298	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
1299	* @param __HANDLE__ ADC handle
1300	* @param __INTERRUPT__ ADC interrupt source to check
1301	* This parameter can be one of the following values:
1302	* @arg @ref ADC_IT_RDY ADC Ready interrupt source
1303	* @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source
1304	* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1305	* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1306	* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1307	* @arg @ref ADC_IT_OVR ADC overrun interrupt source
1308	* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1309	* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1310	* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1311	* @retval State of interruption (SET or RESET)
1312	*/
1313	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1314	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
1315
1316	/**
1317	* @brief Check whether the specified ADC flag is set or not.
1318	* @param __HANDLE__ ADC handle
1319	* @param __FLAG__ ADC flag
1320	* This parameter can be one of the following values:
1321	* @arg @ref ADC_FLAG_RDY ADC Ready flag
1322	* @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag
1323	* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1324	* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1325	* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1326	* @arg @ref ADC_FLAG_OVR ADC overrun flag
1327	* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1328	* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1329	* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1330	* @retval State of flag (TRUE or FALSE).
1331	*/
1332	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
1333	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
1334
1335	/**
1336	* @brief Clear the specified ADC flag.
1337	* @param __HANDLE__ ADC handle
1338	* @param __FLAG__ ADC flag
1339	* This parameter can be one of the following values:
1340	* @arg @ref ADC_FLAG_RDY ADC Ready flag
1341	* @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag
1342	* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1343	* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1344	* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1345	* @arg @ref ADC_FLAG_OVR ADC overrun flag
1346	* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1347	* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1348	* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1349	* @retval None
1350	*/
1351	/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
1352	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1353	(((__HANDLE__)->Instance->ISR) = (__FLAG__))
1354
1355	/**
1356	* @}
1357	*/
1358
1359	/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
1360	* @{
1361	*/
1362
1363	/**
1364	* @brief Helper macro to get ADC channel number in decimal format
1365	* from literals ADC_CHANNEL_x.
1366	* @note Example:
1367	* __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
1368	* will return decimal number "4".
1369	* @note The input can be a value from functions where a channel
1370	* number is returned, either defined with number
1371	* or with bitfield (only one bit must be set).
1372	* @param __CHANNEL__ This parameter can be one of the following values:
1373	* @arg @ref ADC_CHANNEL_0
1374	* @arg @ref ADC_CHANNEL_1
1375	* @arg @ref ADC_CHANNEL_2
1376	* @arg @ref ADC_CHANNEL_3
1377	* @arg @ref ADC_CHANNEL_4
1378	* @arg @ref ADC_CHANNEL_5
1379	* @arg @ref ADC_CHANNEL_6
1380	* @arg @ref ADC_CHANNEL_7
1381	* @arg @ref ADC_CHANNEL_8
1382	* @arg @ref ADC_CHANNEL_9
1383	* @arg @ref ADC_CHANNEL_10
1384	* @arg @ref ADC_CHANNEL_11
1385	* @arg @ref ADC_CHANNEL_12
1386	* @arg @ref ADC_CHANNEL_13
1387	* @arg @ref ADC_CHANNEL_14
1388	* @arg @ref ADC_CHANNEL_15 (1)
1389	* @arg @ref ADC_CHANNEL_16 (1)
1390	* @arg @ref ADC_CHANNEL_17 (1)
1391	* @arg @ref ADC_CHANNEL_18
1392	* @arg @ref ADC_CHANNEL_VREFINT
1393	* @arg @ref ADC_CHANNEL_TEMPSENSOR
1394	* @arg @ref ADC_CHANNEL_VBAT
1395	*
1396	* (1) On STM32G0, parameter can be set in ADC group sequencer
1397	* only if sequencer is set in mode "not fully configurable",
1398	* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1399	* @retval Value between Min_Data=0 and Max_Data=18
1400	*/
1401	#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1402	__LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
1403
1404	/**
1405	* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
1406	* from number in decimal format.
1407	* @note Example:
1408	* __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1409	* will return a data equivalent to "ADC_CHANNEL_4".
1410	* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1411	* @retval Returned value can be one of the following values:
1412	* @arg @ref ADC_CHANNEL_0
1413	* @arg @ref ADC_CHANNEL_1
1414	* @arg @ref ADC_CHANNEL_2
1415	* @arg @ref ADC_CHANNEL_3
1416	* @arg @ref ADC_CHANNEL_4
1417	* @arg @ref ADC_CHANNEL_5
1418	* @arg @ref ADC_CHANNEL_6
1419	* @arg @ref ADC_CHANNEL_7
1420	* @arg @ref ADC_CHANNEL_8
1421	* @arg @ref ADC_CHANNEL_9
1422	* @arg @ref ADC_CHANNEL_10
1423	* @arg @ref ADC_CHANNEL_11
1424	* @arg @ref ADC_CHANNEL_12
1425	* @arg @ref ADC_CHANNEL_13
1426	* @arg @ref ADC_CHANNEL_14
1427	* @arg @ref ADC_CHANNEL_15 (1)
1428	* @arg @ref ADC_CHANNEL_16 (1)
1429	* @arg @ref ADC_CHANNEL_17 (1)
1430	* @arg @ref ADC_CHANNEL_18
1431	* @arg @ref ADC_CHANNEL_VREFINT (2)
1432	* @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
1433	* @arg @ref ADC_CHANNEL_VBAT (2)
1434	*
1435	* (1) On STM32G0, parameter can be set in ADC group sequencer
1436	* only if sequencer is set in mode "not fully configurable",
1437	* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1438	* (2) For ADC channel read back from ADC register,
1439	* comparison with internal channel parameter to be done
1440	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1441	*/
1442	#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1443	__LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
1444
1445	/**
1446	* @brief Helper macro to determine whether the selected channel
1447	* corresponds to literal definitions of driver.
1448	* @note The different literal definitions of ADC channels are:
1449	* - ADC internal channel:
1450	* ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
1451	* - ADC external channel (channel connected to a GPIO pin):
1452	* ADC_CHANNEL_1, ADC_CHANNEL_2, ...
1453	* @note The channel parameter must be a value defined from literal
1454	* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1455	* ADC_CHANNEL_TEMPSENSOR, ...),
1456	* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
1457	* must not be a value from functions where a channel number is
1458	* returned from ADC registers,
1459	* because internal and external channels share the same channel
1460	* number in ADC registers. The differentiation is made only with
1461	* parameters definitions of driver.
1462	* @param __CHANNEL__ This parameter can be one of the following values:
1463	* @arg @ref ADC_CHANNEL_0
1464	* @arg @ref ADC_CHANNEL_1
1465	* @arg @ref ADC_CHANNEL_2
1466	* @arg @ref ADC_CHANNEL_3
1467	* @arg @ref ADC_CHANNEL_4
1468	* @arg @ref ADC_CHANNEL_5
1469	* @arg @ref ADC_CHANNEL_6
1470	* @arg @ref ADC_CHANNEL_7
1471	* @arg @ref ADC_CHANNEL_8
1472	* @arg @ref ADC_CHANNEL_9
1473	* @arg @ref ADC_CHANNEL_10
1474	* @arg @ref ADC_CHANNEL_11
1475	* @arg @ref ADC_CHANNEL_12
1476	* @arg @ref ADC_CHANNEL_13
1477	* @arg @ref ADC_CHANNEL_14
1478	* @arg @ref ADC_CHANNEL_15 (1)
1479	* @arg @ref ADC_CHANNEL_16 (1)
1480	* @arg @ref ADC_CHANNEL_17 (1)
1481	* @arg @ref ADC_CHANNEL_18
1482	* @arg @ref ADC_CHANNEL_VREFINT
1483	* @arg @ref ADC_CHANNEL_TEMPSENSOR
1484	* @arg @ref ADC_CHANNEL_VBAT
1485	*
1486	* (1) On STM32G0, parameter can be set in ADC group sequencer
1487	* only if sequencer is set in mode "not fully configurable",
1488	* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1489	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
1490	* (channel connected to a GPIO pin).
1491	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1492	*/
1493	#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1494	__LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
1495
1496	/**
1497	* @brief Helper macro to convert a channel defined from parameter
1498	* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1499	* ADC_CHANNEL_TEMPSENSOR, ...),
1500	* to its equivalent parameter definition of a ADC external channel
1501	* (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
1502	* @note The channel parameter can be, additionally to a value
1503	* defined from parameter definition of a ADC internal channel
1504	* (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
1505	* a value defined from parameter definition of
1506	* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1507	* or a value from functions where a channel number is returned
1508	* from ADC registers.
1509	* @param __CHANNEL__ This parameter can be one of the following values:
1510	* @arg @ref ADC_CHANNEL_0
1511	* @arg @ref ADC_CHANNEL_1
1512	* @arg @ref ADC_CHANNEL_2
1513	* @arg @ref ADC_CHANNEL_3
1514	* @arg @ref ADC_CHANNEL_4
1515	* @arg @ref ADC_CHANNEL_5
1516	* @arg @ref ADC_CHANNEL_6
1517	* @arg @ref ADC_CHANNEL_7
1518	* @arg @ref ADC_CHANNEL_8
1519	* @arg @ref ADC_CHANNEL_9
1520	* @arg @ref ADC_CHANNEL_10
1521	* @arg @ref ADC_CHANNEL_11
1522	* @arg @ref ADC_CHANNEL_12
1523	* @arg @ref ADC_CHANNEL_13
1524	* @arg @ref ADC_CHANNEL_14
1525	* @arg @ref ADC_CHANNEL_15 (1)
1526	* @arg @ref ADC_CHANNEL_16 (1)
1527	* @arg @ref ADC_CHANNEL_17 (1)
1528	* @arg @ref ADC_CHANNEL_18
1529	* @arg @ref ADC_CHANNEL_VREFINT
1530	* @arg @ref ADC_CHANNEL_TEMPSENSOR
1531	* @arg @ref ADC_CHANNEL_VBAT
1532	*
1533	* (1) On STM32G0, parameter can be set in ADC group sequencer
1534	* only if sequencer is set in mode "not fully configurable",
1535	* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1536	* @retval Returned value can be one of the following values:
1537	* @arg @ref ADC_CHANNEL_0
1538	* @arg @ref ADC_CHANNEL_1
1539	* @arg @ref ADC_CHANNEL_2
1540	* @arg @ref ADC_CHANNEL_3
1541	* @arg @ref ADC_CHANNEL_4
1542	* @arg @ref ADC_CHANNEL_5
1543	* @arg @ref ADC_CHANNEL_6
1544	* @arg @ref ADC_CHANNEL_7
1545	* @arg @ref ADC_CHANNEL_8
1546	* @arg @ref ADC_CHANNEL_9
1547	* @arg @ref ADC_CHANNEL_10
1548	* @arg @ref ADC_CHANNEL_11
1549	* @arg @ref ADC_CHANNEL_12
1550	* @arg @ref ADC_CHANNEL_13
1551	* @arg @ref ADC_CHANNEL_14
1552	* @arg @ref ADC_CHANNEL_15
1553	* @arg @ref ADC_CHANNEL_16
1554	* @arg @ref ADC_CHANNEL_17
1555	* @arg @ref ADC_CHANNEL_18
1556	*/
1557	#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1558	__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
1559
1560	/**
1561	* @brief Helper macro to determine whether the internal channel
1562	* selected is available on the ADC instance selected.
1563	* @note The channel parameter must be a value defined from parameter
1564	* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1565	* ADC_CHANNEL_TEMPSENSOR, ...),
1566	* must not be a value defined from parameter definition of
1567	* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1568	* or a value from functions where a channel number is
1569	* returned from ADC registers,
1570	* because internal and external channels share the same channel
1571	* number in ADC registers. The differentiation is made only with
1572	* parameters definitions of driver.
1573	* @param __ADC_INSTANCE__ ADC instance
1574	* @param __CHANNEL__ This parameter can be one of the following values:
1575	* @arg @ref ADC_CHANNEL_VREFINT
1576	* @arg @ref ADC_CHANNEL_TEMPSENSOR
1577	* @arg @ref ADC_CHANNEL_VBAT
1578	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1579	* Value "1" if the internal channel selected is available on the ADC instance selected.
1580	*/
1581	#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1582	__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
1583
1584	/**
1585	* @brief Helper macro to select the ADC common instance
1586	* to which is belonging the selected ADC instance.
1587	* @note ADC common register instance can be used for:
1588	* - Set parameters common to several ADC instances
1589	* - Multimode (for devices with several ADC instances)
1590	* Refer to functions having argument "ADCxy_COMMON" as parameter.
1591	* @param __ADCx__ ADC instance
1592	* @retval ADC common register instance
1593	*/
1594	#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
1595	__LL_ADC_COMMON_INSTANCE((__ADCx__))
1596
1597	/**
1598	* @brief Helper macro to check if all ADC instances sharing the same
1599	* ADC common instance are disabled.
1600	* @note This check is required by functions with setting conditioned to
1601	* ADC state:
1602	* All ADC instances of the ADC common group must be disabled.
1603	* Refer to functions having argument "ADCxy_COMMON" as parameter.
1604	* @note On devices with only 1 ADC common instance, parameter of this macro
1605	* is useless and can be ignored (parameter kept for compatibility
1606	* with devices featuring several ADC common instances).
1607	* @param __ADCXY_COMMON__ ADC common instance
1608	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1609	* @retval Value "0" if all ADC instances sharing the same ADC common instance
1610	* are disabled.
1611	* Value "1" if at least one ADC instance sharing the same ADC common instance
1612	* is enabled.
1613	*/
1614	#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1615	__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
1616
1617	/**
1618	* @brief Helper macro to define the ADC conversion data full-scale digital
1619	* value corresponding to the selected ADC resolution.
1620	* @note ADC conversion data full-scale corresponds to voltage range
1621	* determined by analog voltage references Vref+ and Vref-
1622	* (refer to reference manual).
1623	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1624	* @arg @ref ADC_RESOLUTION_12B
1625	* @arg @ref ADC_RESOLUTION_10B
1626	* @arg @ref ADC_RESOLUTION_8B
1627	* @arg @ref ADC_RESOLUTION_6B
1628	* @retval ADC conversion data full-scale digital value
1629	*/
1630	#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1631	__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
1632
1633	/**
1634	* @brief Helper macro to convert the ADC conversion data from
1635	* a resolution to another resolution.
1636	* @param __DATA__ ADC conversion data to be converted
1637	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1638	* This parameter can be one of the following values:
1639	* @arg @ref ADC_RESOLUTION_12B
1640	* @arg @ref ADC_RESOLUTION_10B
1641	* @arg @ref ADC_RESOLUTION_8B
1642	* @arg @ref ADC_RESOLUTION_6B
1643	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1644	* This parameter can be one of the following values:
1645	* @arg @ref ADC_RESOLUTION_12B
1646	* @arg @ref ADC_RESOLUTION_10B
1647	* @arg @ref ADC_RESOLUTION_8B
1648	* @arg @ref ADC_RESOLUTION_6B
1649	* @retval ADC conversion data to the requested resolution
1650	*/
1651	#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1652	__ADC_RESOLUTION_CURRENT__,\
1653	__ADC_RESOLUTION_TARGET__) \
1654	__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
1655	(__ADC_RESOLUTION_CURRENT__),\
1656	(__ADC_RESOLUTION_TARGET__))
1657
1658	/**
1659	* @brief Helper macro to calculate the voltage (unit: mVolt)
1660	* corresponding to a ADC conversion data (unit: digital value).
1661	* @note Analog reference voltage (Vref+) must be either known from
1662	* user board environment or can be calculated using ADC measurement
1663	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1664	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1665	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1666	* (unit: digital value).
1667	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1668	* @arg @ref ADC_RESOLUTION_12B
1669	* @arg @ref ADC_RESOLUTION_10B
1670	* @arg @ref ADC_RESOLUTION_8B
1671	* @arg @ref ADC_RESOLUTION_6B
1672	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
1673	*/
1674	#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1675	__ADC_DATA__,\
1676	__ADC_RESOLUTION__) \
1677	__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
1678	(__ADC_DATA__),\
1679	(__ADC_RESOLUTION__))
1680
1681	/**
1682	* @brief Helper macro to calculate analog reference voltage (Vref+)
1683	* (unit: mVolt) from ADC conversion data of internal voltage
1684	* reference VrefInt.
1685	* @note Computation is using VrefInt calibration value
1686	* stored in system memory for each device during production.
1687	* @note This voltage depends on user board environment: voltage level
1688	* connected to pin Vref+.
1689	* On devices with small package, the pin Vref+ is not present
1690	* and internally bonded to pin Vdda.
1691	* @note On this STM32 series, calibration data of internal voltage reference
1692	* VrefInt corresponds to a resolution of 12 bits,
1693	* this is the recommended ADC resolution to convert voltage of
1694	* internal voltage reference VrefInt.
1695	* Otherwise, this macro performs the processing to scale
1696	* ADC conversion data to 12 bits.
1697	* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1698	* of internal voltage reference VrefInt (unit: digital value).
1699	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1700	* @arg @ref ADC_RESOLUTION_12B
1701	* @arg @ref ADC_RESOLUTION_10B
1702	* @arg @ref ADC_RESOLUTION_8B
1703	* @arg @ref ADC_RESOLUTION_6B
1704	* @retval Analog reference voltage (unit: mV)
1705	*/
1706	#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1707	__ADC_RESOLUTION__) \
1708	__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
1709	(__ADC_RESOLUTION__))
1710
1711	/**
1712	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
1713	* from ADC conversion data of internal temperature sensor.
1714	* @note Computation is using temperature sensor calibration values
1715	* stored in system memory for each device during production.
1716	* @note Calculation formula:
1717	* Temperature = ((TS_ADC_DATA - TS_CAL1)
1718	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1719	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1720	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
1721	* Avg_Slope = (TS_CAL2 - TS_CAL1)
1722	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1723	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
1724	* TEMP_DEGC_CAL1 (calibrated in factory)
1725	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
1726	* TEMP_DEGC_CAL2 (calibrated in factory)
1727	* Caution: Calculation relevancy under reserve that calibration
1728	* parameters are correct (address and data).
1729	* To calculate temperature using temperature sensor
1730	* datasheet typical values (generic values less, therefore
1731	* less accurate than calibrated values),
1732	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1733	* @note As calculation input, the analog reference voltage (Vref+) must be
1734	* defined as it impacts the ADC LSB equivalent voltage.
1735	* @note Analog reference voltage (Vref+) must be either known from
1736	* user board environment or can be calculated using ADC measurement
1737	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1738	* @note On this STM32 series, calibration data of temperature sensor
1739	* corresponds to a resolution of 12 bits,
1740	* this is the recommended ADC resolution to convert voltage of
1741	* temperature sensor.
1742	* Otherwise, this macro performs the processing to scale
1743	* ADC conversion data to 12 bits.
1744	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1745	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1746	* temperature sensor (unit: digital value).
1747	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1748	* sensor voltage has been measured.
1749	* This parameter can be one of the following values:
1750	* @arg @ref ADC_RESOLUTION_12B
1751	* @arg @ref ADC_RESOLUTION_10B
1752	* @arg @ref ADC_RESOLUTION_8B
1753	* @arg @ref ADC_RESOLUTION_6B
1754	* @retval Temperature (unit: degree Celsius)
1755	*/
1756	#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1757	__TEMPSENSOR_ADC_DATA__,\
1758	__ADC_RESOLUTION__) \
1759	__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
1760	(__TEMPSENSOR_ADC_DATA__),\
1761	(__ADC_RESOLUTION__))
1762
1763	/**
1764	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
1765	* from ADC conversion data of internal temperature sensor.
1766	* @note Computation is using temperature sensor typical values
1767	* (refer to device datasheet).
1768	* @note Calculation formula:
1769	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1770	* / Avg_Slope + CALx_TEMP
1771	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
1772	* (unit: digital value)
1773	* Avg_Slope = temperature sensor slope
1774	* (unit: uV/Degree Celsius)
1775	* TS_TYP_CALx_VOLT = temperature sensor digital value at
1776	* temperature CALx_TEMP (unit: mV)
1777	* Caution: Calculation relevancy under reserve the temperature sensor
1778	* of the current device has characteristics in line with
1779	* datasheet typical values.
1780	* If temperature sensor calibration values are available on
1781	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1782	* temperature calculation will be more accurate using
1783	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1784	* @note As calculation input, the analog reference voltage (Vref+) must be
1785	* defined as it impacts the ADC LSB equivalent voltage.
1786	* @note Analog reference voltage (Vref+) must be either known from
1787	* user board environment or can be calculated using ADC measurement
1788	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1789	* @note ADC measurement data must correspond to a resolution of 12bits
1790	* (full scale digital value 4095). If not the case, the data must be
1791	* preliminarily rescaled to an equivalent resolution of 12 bits.
1792	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1793	(unit: uV/DegCelsius).
1794	* On STM32G0, refer to device datasheet parameter "Avg_Slope".
1795	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
1796	temperature and Vref+ defined in parameters below) (unit: mV).
1797	* On STM32G0, refer to device datasheet parameter "V30"
1798	(corresponding to TS_CAL1).
1799	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
1800	parameter above) is corresponding (unit: mV)
1801	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1802	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1803	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1804	* This parameter can be one of the following values:
1805	* @arg @ref ADC_RESOLUTION_12B
1806	* @arg @ref ADC_RESOLUTION_10B
1807	* @arg @ref ADC_RESOLUTION_8B
1808	* @arg @ref ADC_RESOLUTION_6B
1809	* @retval Temperature (unit: degree Celsius)
1810	*/
1811	#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1812	__TEMPSENSOR_TYP_CALX_V__,\
1813	__TEMPSENSOR_CALX_TEMP__,\
1814	__VREFANALOG_VOLTAGE__,\
1815	__TEMPSENSOR_ADC_DATA__,\
1816	__ADC_RESOLUTION__) \
1817	__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
1818	(__TEMPSENSOR_TYP_CALX_V__),\
1819	(__TEMPSENSOR_CALX_TEMP__),\
1820	(__VREFANALOG_VOLTAGE__),\
1821	(__TEMPSENSOR_ADC_DATA__),\
1822	(__ADC_RESOLUTION__))
1823
1824	/**
1825	* @}
1826	*/
1827
1828	/**
1829	* @}
1830	*/
1831
1832	/* Include ADC HAL Extended module */
1833	#include "stm32g0xx_hal_adc_ex.h"
1834
1835	/* Exported functions --------------------------------------------------------*/
1836	/** @addtogroup ADC_Exported_Functions
1837	* @{
1838	*/
1839
1840	/** @addtogroup ADC_Exported_Functions_Group1
1841	* @brief Initialization and Configuration functions
1842	* @{
1843	*/
1844	/* Initialization and de-initialization functions ****************************/
1845	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
1846	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
1847	void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
1848	void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
1849
1850	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1851	/* Callbacks Register/UnRegister functions ***********************************/
1852	HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
1853	pADC_CallbackTypeDef pCallback);
1854	HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
1855	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1856	/**
1857	* @}
1858	*/
1859
1860	/** @addtogroup ADC_Exported_Functions_Group2
1861	* @brief IO operation functions
1862	* @{
1863	*/
1864	/* IO operation functions *****************************************************/
1865
1866	/* Blocking mode: Polling */
1867	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
1868	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
1869	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1870	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
1871
1872	/* Non-blocking mode: Interruption */
1873	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
1874	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
1875
1876	/* Non-blocking mode: DMA */
1877	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length);
1878	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
1879
1880	/* ADC retrieve conversion value intended to be used with polling or interruption */
1881	uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
1882
1883	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
1884	void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
1885	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
1886	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
1887	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
1888	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
1889	/**
1890	* @}
1891	*/
1892
1893	/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
1894	* @brief Peripheral Control functions
1895	* @{
1896	*/
1897	/* Peripheral Control functions ***********************************************/
1898	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef hadc, const ADC_ChannelConfTypeDef pConfig);
1899	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
1900	const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
1901
1902	/**
1903	* @}
1904	*/
1905
1906	/* Peripheral State functions *************************************************/
1907	/** @addtogroup ADC_Exported_Functions_Group4
1908	* @{
1909	*/
1910	uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
1911	uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
1912
1913	/**
1914	* @}
1915	*/
1916
1917	/**
1918	* @}
1919	*/
1920
1921	/* Private functions ---------------------------------------------------------*/
1922	HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc);
1923	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
1924	HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
1925
1926	/**
1927	* @}
1928	*/
1929
1930	/**
1931	* @}
1932	*/
1933
1934	/**
1935	* @}
1936	*/
1937
1938	#ifdef __cplusplus
1939	}
1940	#endif
1941
1942
1943	#endif /* STM32G0xx_HAL_ADC_H */

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h

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