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stm32g0xx_hal_flash.h

Last change on this file was 6, checked in by f.jahn, 3 months ago

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_hal_flash.h
4	* @author MCD Application Team
5	* @brief Header file of FLASH HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.
11	*
12	* This software is licensed under terms that can be found in the LICENSE file in
13	* the root directory of this software component.
14	* If no LICENSE file comes with this software, it is provided AS-IS.
15	******************************************************************************
16	*/
17
18	/* Define to prevent recursive inclusion -------------------------------------*/
19	#ifndef STM32G0xx_HAL_FLASH_H
20	#define STM32G0xx_HAL_FLASH_H
21
22	#ifdef __cplusplus
23	extern "C" {
24	#endif
25
26	/* Includes ------------------------------------------------------------------*/
27	#include "stm32g0xx_hal_def.h"
28
29	/** @addtogroup STM32G0xx_HAL_Driver
30	* @{
31	*/
32
33	/** @addtogroup FLASH
34	* @{
35	*/
36
37	/* Exported types ------------------------------------------------------------*/
38	/** @defgroup FLASH_Exported_Types FLASH Exported Types
39	* @{
40	*/
41
42	/**
43	* @brief FLASH Erase structure definition
44	*/
45	typedef struct
46	{
47	uint32_t TypeErase; /*!< Mass erase or page erase.
48	This parameter can be a value of @ref FLASH_Type_Erase */
49	uint32_t Banks; /*!< Select bank to erase.
50	This parameter must be a value of @ref FLASH_Banks
51	(FLASH_BANK_BOTH should be used only for mass erase) */
52	uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled
53	This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
54	uint32_t NbPages; /*!< Number of pages to be erased.
55	This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
56	} FLASH_EraseInitTypeDef;
57
58	/**
59	* @brief FLASH Option Bytes Program structure definition
60	*/
61	typedef struct
62	{
63	uint32_t OptionType; /*!< Option byte to be configured.
64	This parameter can be a combination of the values of @ref FLASH_OB_Type */
65	uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
66	Only one WRP area could be programmed at the same time.
67	This parameter can be value of @ref FLASH_OB_WRP_Area */
68	uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
69	This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/
70	uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
71	This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */
72	uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP).
73	This parameter can be a value of @ref FLASH_OB_Read_Protection */
74	uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
75	This parameter can be a combination of @ref FLASH_OB_USER_Type */
76	uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
77	This parameter can be a combination of
78	@ref FLASH_OB_USER_BOR_ENABLE(*),
79	@ref FLASH_OB_USER_BOR_LEVEL(*),
80	@ref FLASH_OB_USER_RESET_CONFIG(*),
81	@ref FLASH_OB_USER_nRST_STOP,
82	@ref FLASH_OB_USER_nRST_STANDBY,
83	@ref FLASH_OB_USER_nRST_SHUTDOWN(*),
84	@ref FLASH_OB_USER_IWDG_SW,
85	@ref FLASH_OB_USER_IWDG_STOP,
86	@ref FLASH_OB_USER_IWDG_STANDBY,
87	@ref FLASH_OB_USER_WWDG_SW,
88	@ref FLASH_OB_USER_SRAM_PARITY,
89	@ref FLASH_OB_USER_BANK_SWAP(*),
90	@ref FLASH_OB_USER_DUAL_BANK(*),
91	@ref FLASH_OB_USER_nBOOT_SEL,
92	@ref FLASH_OB_USER_nBOOT1,
93	@ref FLASH_OB_USER_nBOOT0,
94	@ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
95	@note () availability depends on devices /
96	#if defined(FLASH_PCROP_SUPPORT)
97	uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
98	This parameter must be a combination of @ref FLASH_OB_PCROP_ZONE
99	and @ref FLASH_OB_PCROP_RDP. Note that once set, Pcrop erase on RDP level 1 regression
100	(PCROP_RDP bit) can not be reset. It will be reset by mass erase */
101	uint32_t PCROP1AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
102	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
103	uint32_t PCROP1AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
104	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
105	uint32_t PCROP1BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
106	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
107	uint32_t PCROP1BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
108	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
109	#if defined(FLASH_DBANK_SUPPORT)
110	uint32_t PCROP2AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
111	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
112	uint32_t PCROP2AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
113	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
114	uint32_t PCROP2BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
115	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
116	uint32_t PCROP2BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block
117	to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/
118	#endif /* FLASH_DBANK_SUPPORT */
119	#endif /* FLASH_PCROP_SUPPORT */
120	#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
121	uint32_t BootEntryPoint; /!< Allow to force a unique boot entry point to Flash or system Flash /
122	uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address.
123	This parameter must be a value between [0] and [FLASH_PAGE_NB],
124	[0] meaning no secure area defined, [1] meaning first page only protected, etc... */
125	#if defined(FLASH_DBANK_SUPPORT)
126	uint32_t SecSize2; /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address.
127	This parameter must be a value between [0] and [FLASH_PAGE_NB],
128	[0] meaning no secure area defined, [1] meaning first page only protected, etc... */
129	#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
130	#endif /* FLASH_DBANK_SUPPORT */
131	} FLASH_OBProgramInitTypeDef;
132
133	/**
134	* @brief FLASH handle Structure definition
135	*/
136	typedef struct
137	{
138	HAL_LockTypeDef Lock; /* FLASH locking object */
139	uint32_t ErrorCode; /* FLASH error code */
140	uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
141	uint32_t Address; /* Internal variable to save address selected for program in IT context */
142	uint32_t Banks; /* Internal variable to save current bank selected during erase in IT context */
143	uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
144	uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
145	} FLASH_ProcessTypeDef;
146
147	/**
148	* @}
149	*/
150
151	/* Exported constants --------------------------------------------------------*/
152	/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
153	* @{
154	*/
155	/** @defgroup FLASH_Keys FLASH Keys
156	* @{
157	*/
158	#define FLASH_KEY1 0x45670123U /!< Flash key1 /
159	#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
160	to unlock the FLASH registers access */
161	#define FLASH_OPTKEY1 0x08192A3BU /!< Flash option byte key1 /
162	#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
163	to allow option bytes operations */
164	/**
165	* @}
166	*/
167
168	/** @defgroup FLASH_Latency FLASH Latency
169	* @{
170	*/
171	#define FLASH_LATENCY_0 0x00000000UL /!< FLASH Zero wait state /
172	#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /!< FLASH One wait state /
173	#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /!< FLASH Two wait states /
174	/**
175	* @}
176	*/
177
178	/** @defgroup FLASH_Flags FLASH Flags Definition
179	* @{
180	*/
181	#define FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_EOP_Pos) /!< FLASH End of operation flag /
182	#define FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_OPERR_Pos) /!< FLASH Operation error flag /
183	#define FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_PROGERR_Pos) /!< FLASH Programming error flag /
184	#define FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_WRPERR_Pos) /!< FLASH Write protection error flag /
185	#define FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_PGAERR_Pos) /!< FLASH Programming alignment error flag /
186	#define FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_SIZERR_Pos) /!< FLASH Size error flag /
187	#define FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_PGSERR_Pos) /!< FLASH Programming sequence error flag /
188	#define FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_MISERR_Pos) /!< FLASH Fast programming data miss error flag /
189	#define FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_FASTERR_Pos) /!< FLASH Fast programming error flag /
190	#if defined(FLASH_PCROP_SUPPORT)
191	#define FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_RDERR_Pos) /!< FLASH PCROP read error flag /
192	#endif /* FLASH_PCROP_SUPPORT */
193	#define FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_OPTVERR_Pos) /!< FLASH Option validity error flag /
194	#define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_BSY1_Pos) /!< FLASH Operation Busy flag for Bank 1 /
195	#if defined(FLASH_DBANK_SUPPORT)
196	#define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_BSY2_Pos) /!< FLASH Operation Busy flag for Bank 2 /
197	#endif /* FLASH_DBANK_SUPPORT */
198	#define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /!< FLASH Operation Busy flag - legacy name for single bank /
199	#define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_CFGBSY_Pos) /!< FLASH Configuration Busy flag /
200	#if defined(FLASH_DBANK_SUPPORT)
201	#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) \| FLASH_SR_PESD_Pos) /!< FLASH Programming/erase operation suspended /
202	#endif /* FLASH_DBANK_SUPPORT */
203	#define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) \| FLASH_ECCR_ECCC_Pos) /!< FLASH ECC correction on bank 1 /
204	#define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) \| FLASH_ECCR_ECCD_Pos) /!< FLASH ECC detection on bank 1 /
205	#if defined(FLASH_DBANK_SUPPORT)
206	#define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) \| FLASH_ECC2R_ECCC_Pos) /!< FLASH ECC correction on bank 2 /
207	#define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) \| FLASH_ECC2R_ECCD_Pos) /!< FLASH ECC detection on bank 2 /
208	#endif /* FLASH_DBANK_SUPPORT */
209	#define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1 /!< FLASH ECC correction - legacy name for single bank /
210	#define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1 /!< FLASH ECC detection - legacy name for single bank /
211	/**
212	* @}
213	*/
214
215	/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
216	* @brief FLASH Interrupt definition
217	* @{
218	*/
219	#define FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) \| FLASH_CR_EOPIE_Pos) /!< End of FLASH Operation Interrupt source /
220	#define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) \| FLASH_CR_ERRIE_Pos) /!< Error Interrupt source /
221	#if defined(FLASH_PCROP_SUPPORT)
222	#define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) \| FLASH_CR_RDERRIE_Pos) /!< PCROP Read Error Interrupt source/
223	#endif /* FLASH_PCROP_SUPPORT */
224	#define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) \| FLASH_ECCR_ECCCIE_Pos) /!< ECC Correction on Bank 1 Interrupt source /
225	#if defined(FLASH_DBANK_SUPPORT)
226	#define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) \| FLASH_ECC2R_ECCCIE_Pos) /!< ECC Correction on Bank 2 Interrupt source /
227	#endif /* FLASH_DBANK_SUPPORT */
228	#define FLASH_IT_ECCC FLASH_IT_ECCC1 /!< ECC Correction - legacy name for single bank /
229	/**
230	* @}
231	*/
232
233	/** @defgroup FLASH_Error FLASH Error
234	* @{
235	*/
236	#define HAL_FLASH_ERROR_NONE 0x00000000U
237	#define HAL_FLASH_ERROR_OP FLASH_SR_OPERR
238	#define HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR
239	#define HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR
240	#define HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR
241	#define HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR
242	#define HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR
243	#define HAL_FLASH_ERROR_MIS FLASH_SR_MISERR
244	#define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR
245	#if defined(FLASH_PCROP_SUPPORT)
246	#define HAL_FLASH_ERROR_RD FLASH_SR_RDERR
247	#endif /* FLASH_PCROP_SUPPORT */
248	#define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR
249	#define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD
250	/**
251	* @}
252	*/
253
254	/** @defgroup FLASH_Type_Erase FLASH Erase Type
255	* @{
256	*/
257	#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /!< Pages erase only /
258	#define FLASH_TYPEERASE_MASS FLASH_CR_MER1 /!< Flash mass erase activation /
259	/**
260	* @}
261	*/
262
263	/** @defgroup FLASH_Banks FLASH Banks
264	* @{
265	*/
266	#define FLASH_BANK_1 FLASH_CR_MER1 /!< Bank 1 /
267	#if defined(FLASH_DBANK_SUPPORT)
268	#define FLASH_BANK_2 FLASH_CR_MER2 /!< Bank 2 /
269	#endif /* FLASH_DBANK_SUPPORT */
270	/**
271	* @}
272	*/
273
274
275	/** @defgroup FLASH_Type_Program FLASH Program Type
276	* @{
277	*/
278	#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /!< Program a double-word (64-bit) at a specified address /
279	#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /!< Fast program a 32 row double-word (64-bit) at a specified address /
280	/**
281	* @}
282	*/
283
284	/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
285	* @{
286	*/
287	#define OPTIONBYTE_WRP 0x00000001U /!< WRP option byte configuration /
288	#define OPTIONBYTE_RDP 0x00000002U /!< RDP option byte configuration /
289	#define OPTIONBYTE_USER 0x00000004U /!< USER option byte configuration /
290	#if defined(FLASH_PCROP_SUPPORT)
291	#define OPTIONBYTE_PCROP 0x00000008U /!< PCROP option byte configuration /
292	#endif /* FLASH_PCROP_SUPPORT */
293	#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
294	#define OPTIONBYTE_SEC 0x00000010U /!< SEC option byte configuration /
295	#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
296
297	#if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT)
298	#define OPTIONBYTE_ALL (OPTIONBYTE_WRP \| OPTIONBYTE_RDP \| OPTIONBYTE_USER \| \
299	OPTIONBYTE_PCROP \| OPTIONBYTE_SEC) /!< All option byte configuration /
300	#else
301	#define OPTIONBYTE_ALL (OPTIONBYTE_WRP \| OPTIONBYTE_RDP \| OPTIONBYTE_USER) /!< All option byte configuration /
302	#endif /* FLASH_PCROP_SUPPORT && FLASH_SECURABLE_MEMORY_SUPPORT */
303	/**
304	* @}
305	*/
306
307	/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
308	* @{
309	*/
310	#define OB_WRPAREA_ZONE_A 0x00000001U /!< Flash Zone A /
311	#define OB_WRPAREA_ZONE_B 0x00000002U /!< Flash Zone B /
312	#if defined(FLASH_DBANK_SUPPORT)
313	#define OB_WRPAREA_ZONE2_A 0x00000004U /!< Flash Bank 2 Zone A /
314	#define OB_WRPAREA_ZONE2_B 0x00000008U /!< Flash Bank 2 Zone B /
315	#endif /* FLASH_DBANK_SUPPORT */
316	/**
317	* @}
318	*/
319
320	/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
321	* @{
322	*/
323	#define OB_RDP_LEVEL_0 0x000000AAU
324	#define OB_RDP_LEVEL_1 0x000000BBU
325	#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2
326	it is no more possible to go back to level 1 or 0 */
327	/**
328	* @}
329	*/
330
331	/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
332	* @{
333	*/
334	#if defined(PWR_BOR_SUPPORT)
335	#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /!< BOR reset enable /
336	#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV \| FLASH_OPTR_BORR_LEV) /!< BOR reset Level /
337	#endif /* PWR_BOR_SUPPORT */
338	#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /!< Reset generated when entering the stop mode /
339	#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /!< Reset generated when entering the standby mode /
340	#if defined(PWR_SHDW_SUPPORT)
341	#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /!< Reset generated when entering the shutdown mode /
342	#endif /* PWR_SHDW_SUPPORT */
343	#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /!< Independent watchdog selection /
344	#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /!< Independent watchdog counter freeze in stop mode /
345	#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /!< Independent watchdog counter freeze in standby mode /
346	#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /!< Window watchdog selection /
347	#if defined(FLASH_DBANK_SUPPORT)
348	#define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK /!< Swap bank memory addresses /
349	#define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK /!< Select single or dual bank (depending of device memory size) /
350	#endif /* FLASH_DBANK_SUPPORT */
351	#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /!< Sram parity check control /
352	#define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL /!< Boot Selection /
353	#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /!< nBoot1 configuration /
354	#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /!< nBoot0 configuration /
355	#if defined(GPIO_NRST_CONFIG_SUPPORT)
356	#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /!< Reset pin configuration /
357	#endif /* GPIO_NRST_CONFIG_SUPPORT */
358	#if defined(FLASH_OPTR_IRHEN)
359	#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /!< Internal reset holder enable /
360	#endif /* FLASH_OPTR_IRHEN */
361
362	#if defined(FLASH_DBANK_SUPPORT)
363	#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
364	#define OB_USER_ALL (OB_USER_BOR_EN \| OB_USER_BOR_LEV \| OB_USER_nRST_STOP \| \
365	OB_USER_nRST_STDBY \| OB_USER_nRST_SHDW \| OB_USER_IWDG_SW \| \
366	OB_USER_IWDG_STOP \| OB_USER_IWDG_STDBY \| OB_USER_WWDG_SW \| \
367	OB_USER_BANK_SWAP \| OB_USER_DUAL_BANK \| \
368	OB_USER_RAM_PARITY_CHECK \| OB_USER_nBOOT_SEL \| OB_USER_nBOOT1 \| \
369	OB_USER_nBOOT0 \| OB_USER_NRST_MODE \| OB_USER_INPUT_RESET_HOLDER) /!< all option bits /
370	#else
371	#define OB_USER_ALL ( OB_USER_nRST_STOP \| \
372	OB_USER_nRST_STDBY \| OB_USER_IWDG_SW \| \
373	OB_USER_IWDG_STOP \| OB_USER_IWDG_STDBY \| OB_USER_WWDG_SW \| \
374	OB_USER_BANK_SWAP \| OB_USER_DUAL_BANK \| \
375	OB_USER_RAM_PARITY_CHECK \| OB_USER_nBOOT_SEL \| OB_USER_nBOOT1 \| \
376	OB_USER_nBOOT0) /!< all option bits /
377	#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
378	#else
379	#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT)
380	#define OB_USER_ALL (OB_USER_BOR_EN \| OB_USER_BOR_LEV \| OB_USER_nRST_STOP \| \
381	OB_USER_nRST_STDBY \| OB_USER_nRST_SHDW \| OB_USER_IWDG_SW \| \
382	OB_USER_IWDG_STOP \| OB_USER_IWDG_STDBY \| OB_USER_WWDG_SW \| \
383	OB_USER_RAM_PARITY_CHECK \| OB_USER_nBOOT_SEL \| OB_USER_nBOOT1 \| \
384	OB_USER_nBOOT0 \| OB_USER_NRST_MODE \| OB_USER_INPUT_RESET_HOLDER) /!< all option bits /
385	#else
386	#define OB_USER_ALL ( OB_USER_nRST_STOP \| \
387	OB_USER_nRST_STDBY \| OB_USER_IWDG_SW \| \
388	OB_USER_IWDG_STOP \| OB_USER_IWDG_STDBY \| OB_USER_WWDG_SW \| \
389	OB_USER_RAM_PARITY_CHECK \| OB_USER_nBOOT_SEL \| OB_USER_nBOOT1 \| \
390	OB_USER_nBOOT0) /!< all option bits /
391	#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */
392	#endif /* FLASH_DBANK_SUPPORT */
393	/**
394	* @}
395	*/
396
397	#if defined(PWR_BOR_SUPPORT)
398	/** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable
399	* @{
400	*/
401	#define OB_BOR_DISABLE 0x00000000U /!< BOR Reset set to default /
402	#define OB_BOR_ENABLE FLASH_OPTR_BOR_EN /!< Use option byte to define BOR thresholds /
403	/**
404	* @}
405	*/
406
407	/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
408	* @{
409	*/
410	#define OB_BOR_LEVEL_FALLING_0 0x00000000U /!< BOR falling level 1 with threshold around 2.0V /
411	#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /!< BOR falling level 2 with threshold around 2.2V /
412	#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /!< BOR falling level 3 with threshold around 2.5V /
413	#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 \| FLASH_OPTR_BORF_LEV_1) /!< BOR falling level 4 with threshold around 2.8V /
414	#define OB_BOR_LEVEL_RISING_0 0x00000000U /!< BOR rising level 1 with threshold around 2.1V /
415	#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /!< BOR rising level 2 with threshold around 2.3V /
416	#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /!< BOR rising level 3 with threshold around 2.6V /
417	#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 \| FLASH_OPTR_BORR_LEV_1) /!< BOR rising level 4 with threshold around 2.9V /
418	/**
419	* @}
420	*/
421	#endif /* PWR_BOR_SUPPORT */
422
423	/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
424	* @{
425	*/
426	#define OB_STOP_RST 0x00000000U /!< Reset generated when entering the stop mode /
427	#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /!< No reset generated when entering the stop mode /
428	/**
429	* @}
430	*/
431
432	/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
433	* @{
434	*/
435	#define OB_STANDBY_RST 0x00000000U /!< Reset generated when entering the standby mode /
436	#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /!< No reset generated when entering the standby mode /
437	/**
438	* @}
439	*/
440
441	#if defined(PWR_SHDW_SUPPORT)
442	/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
443	* @{
444	*/
445	#define OB_SHUTDOWN_RST 0x00000000U /!< Reset generated when entering the shutdown mode /
446	#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /!< No reset generated when entering the shutdown mode /
447	/**
448	* @}
449	*/
450	#endif /* PWR_SHDW_SUPPORT */
451
452	/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
453	* @{
454	*/
455	#define OB_IWDG_HW 0x00000000U /!< Hardware independent watchdog /
456	#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /!< Software independent watchdog /
457	/**
458	* @}
459	*/
460
461	/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
462	* @{
463	*/
464	#define OB_IWDG_STOP_FREEZE 0x00000000U /!< Independent watchdog counter is frozen in Stop mode /
465	#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /!< Independent watchdog counter is running in Stop mode /
466	/**
467	* @}
468	*/
469
470	/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
471	* @{
472	*/
473	#define OB_IWDG_STDBY_FREEZE 0x00000000U /!< Independent watchdog counter is frozen in Standby mode /
474	#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /!< Independent watchdog counter is running in Standby mode /
475	/**
476	* @}
477	*/
478
479	/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
480	* @{
481	*/
482	#define OB_WWDG_HW 0x00000000U /!< Hardware window watchdog /
483	#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /!< Software window watchdog /
484	/**
485	* @}
486	*/
487
488	#if defined(FLASH_DBANK_SUPPORT)
489	/** @defgroup FLASH_OB_USER_BANK_SWAP FLASH Option Bytes User bank swap Type
490	* @{
491	*/
492	#define OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U /!< Enable bank swap /
493	#define OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK /!< Disable bank swap /
494	/**
495	* @}
496	*/
497
498	/** @defgroup FLASH_OB_USER_DUAL_BANK FLASH Option Bytes User dual bank enable Type
499	* @{
500	*/
501	#define OB_USER_DUALBANK_DISABLE 0x00000000U /!< Disable dual bank /
502	#define OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK /!< Enable dual bank /
503	/**
504	* @}
505	*/
506	#endif /* FLASH_DBANK_SUPPORT */
507
508	/** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity
509	* @{
510	*/
511	#define OB_SRAM_PARITY_ENABLE 0x00000000U /!< Sram parity enable /
512	#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK /!< Sram parity disable /
513	/**
514	* @}
515	*/
516
517	/** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection
518	* @{
519	*/
520	#define OB_BOOT0_FROM_PIN 0x00000000U /!< BOOT0 signal is defined by PA14/BOOT0 pin value /
521	#define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL /!< BOOT0 signal is defined by nBOOT0 option bit /
522	/**
523	* @}
524	*/
525
526	/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
527	* @{
528	*/
529	#define OB_BOOT1_SRAM 0x00000000U /!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) /
530	#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /!< System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) /
531	/**
532	* @}
533	*/
534
535	/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
536	* @{
537	*/
538	#define OB_nBOOT0_RESET 0x00000000U /!< nBOOT0 = 0 /
539	#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /!< nBOOT0 = 1 /
540	/**
541	* @}
542	*/
543
544	#if defined(GPIO_NRST_CONFIG_SUPPORT)
545	/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit
546	* @{
547	*/
548	#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /!< Reset pin is in Reset input mode only /
549	#define OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /!< Reset pin is in GPIO mode mode only /
550	#define OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /!< Reset pin is in reset input and output mode /
551	/**
552	* @}
553	*/
554	#endif /* GPIO_NRST_CONFIG_SUPPORT */
555
556	#if defined(FLASH_OPTR_IRHEN)
557	/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
558	* @{
559	*/
560	#define OB_IRH_ENABLE 0x00000000U /!< Internal Reset handler enable /
561	#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /!< Internal Reset handler disable /
562	/**
563	* @}
564	*/
565	#endif /* FLASH_OPTR_IRHEN */
566
567	#if defined(FLASH_PCROP_SUPPORT)
568	/** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE
569	* @{
570	*/
571	#define OB_PCROP_ZONE_A 0x00000001U /!< PCROP Zone A /
572	#define OB_PCROP_ZONE_B 0x00000002U /!< PCROP Zone B /
573	#if defined(FLASH_DBANK_SUPPORT)
574	#define OB_PCROP_ZONE2_A 0x00000004U /!< PCROP Bank 2 Zone A /
575	#define OB_PCROP_ZONE2_B 0x00000008U /!< PCROP Bank 2 Zone B /
576	#endif /* FLASH_DBANK_SUPPORT */
577	/**
578	* @}
579	*/
580
581	/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
582	* @{
583	*/
584	#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
585	is decreased from Level 1 to Level 0 */
586	#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
587	decreased from Level 1 to Level 0 (full mass erase).
588	Once this bit is set only, it will be reset by mass erase */
589	/**
590	* @}
591	*/
592	#endif /* FLASH_PCROP_SUPPORT */
593
594	#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
595	/** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock
596	* @{
597	*/
598	#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U /!< Boot entry is free /
599	#define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK /!< Boot entry is forced to Flash or System Flash /
600	/**
601	* @}
602	*/
603	#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
604
605	/**
606	* @}
607	*/
608
609	/* Exported macros -----------------------------------------------------------*/
610	/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
611	* @brief macros to control FLASH features
612	* @{
613	*/
614
615	/**
616	* @brief Set the FLASH Latency.
617	* @param __LATENCY__ FLASH Latency
618	* This parameter can be one of the following values :
619	* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
620	* @arg @ref FLASH_LATENCY_1 FLASH One wait state
621	* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
622	* @retval None
623	*/
624	#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
625
626	/**
627	* @brief Get the FLASH Latency.
628	* @retval FLASH Latency
629	* Returned value can be one of the following values :
630	* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
631	* @arg @ref FLASH_LATENCY_1 FLASH One wait state
632	* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
633	*/
634	#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
635
636	/**
637	* @brief Enable the FLASH prefetch buffer.
638	* @retval None
639	*/
640	#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
641
642	/**
643	* @brief Disable the FLASH prefetch buffer.
644	* @retval None
645	*/
646	#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
647
648	/**
649	* @brief Enable the FLASH instruction cache.
650	* @retval none
651	*/
652	#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
653
654	/**
655	* @brief Disable the FLASH instruction cache.
656	* @retval none
657	*/
658	#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
659
660	/**
661	* @brief Reset the FLASH instruction Cache.
662	* @note This function must be used only when the Instruction Cache is disabled.
663	* @retval None
664	*/
665	#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
666	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
667	} while (0U)
668	/**
669	* @}
670	*/
671
672	/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
673	* @brief macros to handle FLASH interrupts
674	* @{
675	*/
676
677	/**
678	* @brief Enable the specified FLASH interrupt.
679	* @param __INTERRUPT__ FLASH interrupt
680	* This parameter can be one of the following values :
681	* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
682	* @arg @ref FLASH_IT_OPERR Error Interrupt
683	* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*)
684	* @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
685	* @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
686	* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
687	* @note (*) availability depends on devices
688	* @retval none
689	*/
690	#if defined(FLASH_DBANK_SUPPORT)
691	#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
692	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
693	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
694	} while(0U)
695	#else
696	#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
697	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
698	} while(0U)
699	#endif /* FLASH_DBANK_SUPPORT */
700
701	/**
702	* @brief Disable the specified FLASH interrupt.
703	* @param __INTERRUPT__ FLASH interrupt
704	* This parameter can be one of the following values :
705	* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
706	* @arg @ref FLASH_IT_OPERR Error Interrupt
707	* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*)
708	* @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1
709	* @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*)
710	* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank
711	* @note (*) availability depends on devices
712	* @retval none
713	*/
714	#if defined(FLASH_DBANK_SUPPORT)
715	#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
716	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
717	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
718	} while(0U)
719	#else
720	#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
721	else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \
722	} while(0U)
723	#endif /* FLASH_DBANK_SUPPORT */
724
725	/**
726	* @brief Check whether the specified FLASH flag is set or not.
727	* @param __FLAG__ specifies the FLASH flag to check.
728	* This parameter can be one of the following values :
729	* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
730	* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
731	* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
732	* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
733	* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
734	* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
735	* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
736	* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
737	* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
738	* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag(*)
739	* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
740	* @arg @ref FLASH_FLAG_BSY1 FLASH bank 1 write/erase operations in progress flag
741	* @arg @ref FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*)
742	* @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag - legacy name for single bank
743	* @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used.
744	* @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
745	* @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
746	* @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
747	* @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
748	* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
749	* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
750	* @note (*) availability depends on devices
751	* @retval The state of FLASH_FLAG (SET or RESET).
752	*/
753	#if defined(FLASH_DBANK_SUPPORT)
754	#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
755	(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
756	((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
757	(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
758	(READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)))
759	#else
760	#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \
761	(READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \
762	(READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))
763	#endif /* FLASH_DBANK_SUPPORT */
764
765	/**
766	* @brief Clear the FLASH pending flag.
767	* @param __FLAG__ specifies the FLASH flag to clear.
768	* This parameter can be one of the following values :
769	* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
770	* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
771	* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
772	* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
773	* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
774	* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
775	* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
776	* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
777	* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
778	* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
779	* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
780	* @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected
781	* @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1
782	* @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*)
783	* @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*)
784	* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank
785	* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank
786	* @note (*) availability depends on devices
787	* @retval None
788	*/
789	#if defined(FLASH_DBANK_SUPPORT)
790	#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \
791	else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR \|= (1uL << ((__FLAG__) & 0x1Fu)); } \
792	else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R \|= (1uL << ((__FLAG__) & 0x1Fu)); } \
793	} while(0U)
794	#else
795	#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \
796	else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR \|= (1uL << ((__FLAG__) & 0x1Fu)); } \
797	} while(0U)
798	#endif /* FLASH_DBANK_SUPPORT */
799	/**
800	* @}
801	*/
802
803	/* Include FLASH HAL Extended module */
804	#include "stm32g0xx_hal_flash_ex.h"
805	/* Exported variables --------------------------------------------------------*/
806	/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
807	* @{
808	*/
809	extern FLASH_ProcessTypeDef pFlash;
810	/**
811	* @}
812	*/
813
814	/* Exported functions --------------------------------------------------------*/
815	/** @addtogroup FLASH_Exported_Functions
816	* @{
817	*/
818
819	/* Program operation functions ***********************************************/
820	/** @addtogroup FLASH_Exported_Functions_Group1
821	* @{
822	*/
823	HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
824	HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
825	/* FLASH IRQ handler method */
826	void HAL_FLASH_IRQHandler(void);
827	/* Callbacks in non blocking modes */
828	void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
829	void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
830	/**
831	* @}
832	*/
833
834	/* Peripheral Control functions **********************************************/
835	/** @addtogroup FLASH_Exported_Functions_Group2
836	* @{
837	*/
838	HAL_StatusTypeDef HAL_FLASH_Unlock(void);
839	HAL_StatusTypeDef HAL_FLASH_Lock(void);
840	/* Option bytes control */
841	HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
842	HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
843	HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
844	/**
845	* @}
846	*/
847
848	/* Peripheral State functions ************************************************/
849	/** @addtogroup FLASH_Exported_Functions_Group3
850	* @{
851	*/
852	uint32_t HAL_FLASH_GetError(void);
853	/**
854	* @}
855	*/
856
857	/**
858	* @}
859	*/
860
861	/* Private types --------------------------------------------------------*/
862	/** @defgroup FLASH_Private_types FLASH Private Types
863	* @{
864	*/
865	HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
866	/**
867	* @}
868	*/
869
870	/* Private constants --------------------------------------------------------*/
871	/** @defgroup FLASH_Private_Constants FLASH Private Constants
872	* @{
873	*/
874	#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
875
876	#if defined(FLASH_DBANK_SUPPORT)
877	#define OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U) /!< Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence /
878	#define FLASH_SALES_TYPE_Pos (24U)
879	#define FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos) /!< 0x000001E0 /
880	#define FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos) /!< 0x01000000 /
881	#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /!< 0x02000000 /
882	#define FLASH_SALES_VALUE ((((uint32_t )PACKAGE_BASE)) & (FLASH_SALES_TYPE))
883	#define OB_DUAL_BANK_VALUE ((((uint32_t )OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK))
884	#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U)\
885	\|\| ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U)
886	#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /!< FLASH Bank Size. Divided by 2 if 2 Banks /
887	#else /* FLASH_DBANK_SUPPORT */
888	#define FLASH_BANK_SIZE (FLASH_SIZE) /!< FLASH Bank Size /
889	#endif /* FLASH_DBANK_SUPPORT */
890
891	#define FLASH_PAGE_SIZE 0x00000800U /!< FLASH Page Size, 2 KBytes /
892	#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */
893	#define FLASH_TIMEOUT_VALUE 1000U /!< FLASH Execution Timeout, 1 s /
894	#define FLASH_TYPENONE 0x00000000U /!< No programming Procedure On Going /
895
896	#if defined(FLASH_PCROP_SUPPORT)
897	#define FLASH_SR_ERRORS (FLASH_SR_OPERR \| FLASH_SR_PROGERR \| FLASH_SR_WRPERR \| \
898	FLASH_SR_PGAERR \| FLASH_SR_SIZERR \| FLASH_SR_PGSERR \| \
899	FLASH_SR_MISERR \| FLASH_SR_FASTERR \| FLASH_SR_RDERR \| \
900	FLASH_SR_OPTVERR) /!< All SR error flags /
901	#else
902	#define FLASH_SR_ERRORS (FLASH_SR_OPERR \| FLASH_SR_PROGERR \| FLASH_SR_WRPERR \| \
903	FLASH_SR_PGAERR \| FLASH_SR_SIZERR \| FLASH_SR_PGSERR \| \
904	FLASH_SR_MISERR \| FLASH_SR_FASTERR \| \
905	FLASH_SR_OPTVERR) /!< All SR error flags /
906	#endif /* FLASH_PCROP_SUPPORT */
907
908	#if defined(FLASH_DBANK_SUPPORT)
909	#define FLASH_SR_CLEAR (FLASH_SR_ERRORS \| FLASH_SR_EOP \| FLASH_SR_PESD)
910	#else
911	#define FLASH_SR_CLEAR (FLASH_SR_ERRORS \| FLASH_SR_EOP)
912	#endif /* FLASH_DBANK_SUPPORT */
913
914	/* Internal defines for HAL macro usage */
915	#define FLASH_FLAG_REG_POS 16u
916	#define FLASH_FLAG_SR_ID 1u
917	#define FLASH_FLAG_CR_ID 2u
918	#define FLASH_FLAG_ECCR1_ID 4u
919	#define FLASH_FLAG_ECCR2_ID 8u
920
921	/**
922	* @}
923	*/
924
925	/* Private macros ------------------------------------------------------------*/
926	/** @defgroup FLASH_Private_Macros FLASH Private Macros
927	* @{
928	*/
929	#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
930	&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
931
932	#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
933	&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL)))
934	#if defined(FLASH_DBANK_SUPPORT)
935	#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\
936	&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
937	#endif /* FLASH_DBANK_SUPPORT */
938
939	#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
940	&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL)))
941
942	#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U)\
943	&& ((__ADDRESS__) <= (0x1FFF7400U - 8UL)))
944
945	#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\
946	\|\| (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__)))
947
948	#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\
949	&& ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL)))
950
951	#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB)
952
953	#if defined(FLASH_DBANK_SUPPORT)
954	#define IS_FLASH_BANK(__BANK__) \
955	((FLASH_BANK_NB == 2U) ? \
956	(((__BANK__) == FLASH_BANK_1) \|\| \
957	((__BANK__) == FLASH_BANK_2) \|\| \
958	((__BANK__) == (FLASH_BANK_2 \| FLASH_BANK_1))): \
959	((__BANK__) == FLASH_BANK_1))
960	#else
961	#define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1)
962	#endif /* FLASH_DBANK_SUPPORT */
963
964	#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) \|\| \
965	((__VALUE__) == FLASH_TYPEERASE_MASS))
966
967	#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) \|\| \
968	((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
969
970	#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \
971	(((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U))
972
973	#if defined(FLASH_DBANK_SUPPORT)
974	#define IS_OB_WRPAREA(__VALUE__) \
975	((FLASH_BANK_NB == 2U) ? \
976	(((__VALUE__) == OB_WRPAREA_ZONE_A) \|\| ((__VALUE__) == OB_WRPAREA_ZONE_B) \|\| \
977	((__VALUE__) == OB_WRPAREA_ZONE2_A) \|\| ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \
978	(((__VALUE__) == OB_WRPAREA_ZONE_A) \|\| ((__VALUE__) == OB_WRPAREA_ZONE_B)))
979	#else
980	#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A)\
981	\|\| ((__VALUE__) == OB_WRPAREA_ZONE_B))
982	#endif /* FLASH_DBANK_SUPPORT */
983
984	#define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) \|\|\
985	((__LEVEL__) == OB_RDP_LEVEL_1) \|\|\
986	((__LEVEL__) == OB_RDP_LEVEL_2))
987
988	#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \
989	(((__TYPE__) & ~OB_USER_ALL) == 0x00U))
990
991	#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U)
992
993	#if defined(FLASH_PCROP_SUPPORT)
994	#if defined(FLASH_DBANK_SUPPORT)
995	#define IS_OB_PCROP_CONFIG(__CONFIG__) \
996	((FLASH_BANK_NB == 2U) ? \
997	(((__CONFIG__) & ~(OB_PCROP_ZONE_A \| OB_PCROP_ZONE_B \| \
998	OB_PCROP_ZONE2_A \| OB_PCROP_ZONE2_B \| OB_PCROP_RDP_ERASE)) == 0x00U): \
999	(((__CONFIG__) & ~(OB_PCROP_ZONE_A \| OB_PCROP_ZONE_B \| OB_PCROP_RDP_ERASE)) == 0x00U))
1000	#else
1001	#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__)\
1002	& ~(OB_PCROP_ZONE_A \| OB_PCROP_ZONE_B \| OB_PCROP_RDP_ERASE)) == 0x00U)
1003	#endif /* FLASH_DBANK_SUPPORT */
1004	#endif /* FLASH_PCROP_SUPPORT */
1005
1006	#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
1007	#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\
1008	\|\| ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH))
1009
1010	#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U))
1011	#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
1012
1013	#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) \|\| \
1014	((__LATENCY__) == FLASH_LATENCY_1) \|\| \
1015	((__LATENCY__) == FLASH_LATENCY_2))
1016	/**
1017	* @}
1018	*/
1019
1020	/**
1021	* @}
1022	*/
1023
1024	/**
1025	* @}
1026	*/
1027
1028	#ifdef __cplusplus
1029	}
1030	#endif
1031
1032	#endif /* STM32G0xx_HAL_FLASH_H */
1033

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h

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