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stm32g0xx_hal_tim.h

Last change on this file was 6, checked in by f.jahn, 3 months ago

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_hal_tim.h
4	* @author MCD Application Team
5	* @brief Header file of TIM HAL module.
6	******************************************************************************
7	* @attention
8	*
9	* Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.
11	*
12	* This software is licensed under terms that can be found in the LICENSE file
13	* in the root directory of this software component.
14	* If no LICENSE file comes with this software, it is provided AS-IS.
15	*
16	******************************************************************************
17	*/
18
19	/* Define to prevent recursive inclusion -------------------------------------*/
20	#ifndef STM32G0xx_HAL_TIM_H
21	#define STM32G0xx_HAL_TIM_H
22
23	#ifdef __cplusplus
24	extern "C" {
25	#endif
26
27	/* Includes ------------------------------------------------------------------*/
28	#include "stm32g0xx_hal_def.h"
29
30	/** @addtogroup STM32G0xx_HAL_Driver
31	* @{
32	*/
33
34	/** @addtogroup TIM
35	* @{
36	*/
37
38	/* Exported types ------------------------------------------------------------*/
39	/** @defgroup TIM_Exported_Types TIM Exported Types
40	* @{
41	*/
42
43	/**
44	* @brief TIM Time base Configuration Structure definition
45	*/
46	typedef struct
47	{
48	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
49	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
50
51	uint32_t CounterMode; /*!< Specifies the counter mode.
52	This parameter can be a value of @ref TIM_Counter_Mode */
53
54	uint32_t Period; /*!< Specifies the period value to be loaded into the active
55	Auto-Reload Register at the next update event.
56	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
57
58	uint32_t ClockDivision; /*!< Specifies the clock division.
59	This parameter can be a value of @ref TIM_ClockDivision */
60
61	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
62	reaches zero, an update event is generated and counting restarts
63	from the RCR value (N).
64	This means in PWM mode that (N+1) corresponds to:
65	- the number of PWM periods in edge-aligned mode
66	- the number of half PWM period in center-aligned mode
67	GP timers: this parameter must be a number between Min_Data = 0x00 and
68	Max_Data = 0xFF.
69	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
70	Max_Data = 0xFFFF. */
71
72	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
73	This parameter can be a value of @ref TIM_AutoReloadPreload */
74	} TIM_Base_InitTypeDef;
75
76	/**
77	* @brief TIM Output Compare Configuration Structure definition
78	*/
79	typedef struct
80	{
81	uint32_t OCMode; /*!< Specifies the TIM mode.
82	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
83
84	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
85	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
86
87	uint32_t OCPolarity; /*!< Specifies the output polarity.
88	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
89
90	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
91	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
92	@note This parameter is valid only for timer instances supporting break feature. */
93
94	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
95	This parameter can be a value of @ref TIM_Output_Fast_State
96	@note This parameter is valid only in PWM1 and PWM2 mode. */
97
98
99	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
100	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
101	@note This parameter is valid only for timer instances supporting break feature. */
102
103	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
104	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
105	@note This parameter is valid only for timer instances supporting break feature. */
106	} TIM_OC_InitTypeDef;
107
108	/**
109	* @brief TIM One Pulse Mode Configuration Structure definition
110	*/
111	typedef struct
112	{
113	uint32_t OCMode; /*!< Specifies the TIM mode.
114	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
115
116	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
117	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
118
119	uint32_t OCPolarity; /*!< Specifies the output polarity.
120	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
121
122	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
123	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
124	@note This parameter is valid only for timer instances supporting break feature. */
125
126	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
127	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
128	@note This parameter is valid only for timer instances supporting break feature. */
129
130	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
131	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
132	@note This parameter is valid only for timer instances supporting break feature. */
133
134	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
135	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
136
137	uint32_t ICSelection; /*!< Specifies the input.
138	This parameter can be a value of @ref TIM_Input_Capture_Selection */
139
140	uint32_t ICFilter; /*!< Specifies the input capture filter.
141	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
142	} TIM_OnePulse_InitTypeDef;
143
144	/**
145	* @brief TIM Input Capture Configuration Structure definition
146	*/
147	typedef struct
148	{
149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
151
152	uint32_t ICSelection; /*!< Specifies the input.
153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
154
155	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
156	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
157
158	uint32_t ICFilter; /*!< Specifies the input capture filter.
159	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
160	} TIM_IC_InitTypeDef;
161
162	/**
163	* @brief TIM Encoder Configuration Structure definition
164	*/
165	typedef struct
166	{
167	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
168	This parameter can be a value of @ref TIM_Encoder_Mode */
169
170	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
171	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
172
173	uint32_t IC1Selection; /*!< Specifies the input.
174	This parameter can be a value of @ref TIM_Input_Capture_Selection */
175
176	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
177	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
178
179	uint32_t IC1Filter; /*!< Specifies the input capture filter.
180	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
181
182	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
183	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
184
185	uint32_t IC2Selection; /*!< Specifies the input.
186	This parameter can be a value of @ref TIM_Input_Capture_Selection */
187
188	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
189	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
190
191	uint32_t IC2Filter; /*!< Specifies the input capture filter.
192	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
193	} TIM_Encoder_InitTypeDef;
194
195	/**
196	* @brief Clock Configuration Handle Structure definition
197	*/
198	typedef struct
199	{
200	uint32_t ClockSource; /*!< TIM clock sources
201	This parameter can be a value of @ref TIM_Clock_Source */
202	uint32_t ClockPolarity; /*!< TIM clock polarity
203	This parameter can be a value of @ref TIM_Clock_Polarity */
204	uint32_t ClockPrescaler; /*!< TIM clock prescaler
205	This parameter can be a value of @ref TIM_Clock_Prescaler */
206	uint32_t ClockFilter; /*!< TIM clock filter
207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208	} TIM_ClockConfigTypeDef;
209
210	/**
211	* @brief TIM Clear Input Configuration Handle Structure definition
212	*/
213	typedef struct
214	{
215	uint32_t ClearInputState; /*!< TIM clear Input state
216	This parameter can be ENABLE or DISABLE */
217	uint32_t ClearInputSource; /*!< TIM clear Input sources
218	This parameter can be a value of @ref TIM_ClearInput_Source */
219	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
220	This parameter can be a value of @ref TIM_ClearInput_Polarity */
221	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
222	This parameter must be 0: When OCRef clear feature is used with ETR source,
223	ETR prescaler must be off */
224	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
226	} TIM_ClearInputConfigTypeDef;
227
228	/**
229	* @brief TIM Master configuration Structure definition
230	* @note Advanced timers provide TRGO2 internal line which is redirected
231	* to the ADC
232	*/
233	typedef struct
234	{
235	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
236	This parameter can be a value of @ref TIM_Master_Mode_Selection */
237	uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
238	This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
239	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
240	This parameter can be a value of @ref TIM_Master_Slave_Mode
241	@note When the Master/slave mode is enabled, the effect of
242	an event on the trigger input (TRGI) is delayed to allow a
243	perfect synchronization between the current timer and its
244	slaves (through TRGO). It is not mandatory in case of timer
245	synchronization mode. */
246	} TIM_MasterConfigTypeDef;
247
248	/**
249	* @brief TIM Slave configuration Structure definition
250	*/
251	typedef struct
252	{
253	uint32_t SlaveMode; /*!< Slave mode selection
254	This parameter can be a value of @ref TIM_Slave_Mode */
255	uint32_t InputTrigger; /*!< Input Trigger source
256	This parameter can be a value of @ref TIM_Trigger_Selection */
257	uint32_t TriggerPolarity; /*!< Input Trigger polarity
258	This parameter can be a value of @ref TIM_Trigger_Polarity */
259	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
260	This parameter can be a value of @ref TIM_Trigger_Prescaler */
261	uint32_t TriggerFilter; /*!< Input trigger filter
262	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
263
264	} TIM_SlaveConfigTypeDef;
265
266	/**
267	* @brief TIM Break input(s) and Dead time configuration Structure definition
268	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
269	* filter and polarity.
270	*/
271	typedef struct
272	{
273	uint32_t OffStateRunMode; /!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state /
274
275	uint32_t OffStateIDLEMode; /!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state /
276
277	uint32_t LockLevel; /!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level /
278
279	uint32_t DeadTime; /!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF /
280
281	uint32_t BreakState; /!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable /
282
283	uint32_t BreakPolarity; /!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity /
284
285	uint32_t BreakFilter; /!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF /
286
287	uint32_t BreakAFMode; /!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode /
288
289	uint32_t Break2State; /!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable /
290
291	uint32_t Break2Polarity; /!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity /
292
293	uint32_t Break2Filter; /!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF /
294
295	uint32_t Break2AFMode; /!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode /
296
297	uint32_t AutomaticOutput; /!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset /
298
299	} TIM_BreakDeadTimeConfigTypeDef;
300
301	/**
302	* @brief HAL State structures definition
303	*/
304	typedef enum
305	{
306	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
307	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
308	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
309	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
310	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
311	} HAL_TIM_StateTypeDef;
312
313	/**
314	* @brief TIM Channel States definition
315	*/
316	typedef enum
317	{
318	HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /!< TIM Channel initial state /
319	HAL_TIM_CHANNEL_STATE_READY = 0x01U, /!< TIM Channel ready for use /
320	HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /!< An internal process is ongoing on the TIM channel /
321	} HAL_TIM_ChannelStateTypeDef;
322
323	/**
324	* @brief DMA Burst States definition
325	*/
326	typedef enum
327	{
328	HAL_DMA_BURST_STATE_RESET = 0x00U, /!< DMA Burst initial state /
329	HAL_DMA_BURST_STATE_READY = 0x01U, /!< DMA Burst ready for use /
330	HAL_DMA_BURST_STATE_BUSY = 0x02U, /!< Ongoing DMA Burst /
331	} HAL_TIM_DMABurstStateTypeDef;
332
333	/**
334	* @brief HAL Active channel structures definition
335	*/
336	typedef enum
337	{
338	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
339	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
340	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
341	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
342	HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /!< The active channel is 5 /
343	HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /!< The active channel is 6 /
344	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
345	} HAL_TIM_ActiveChannel;
346
347	/**
348	* @brief TIM Time Base Handle Structure definition
349	*/
350	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
351	typedef struct __TIM_HandleTypeDef
352	#else
353	typedef struct
354	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
355	{
356	TIM_TypeDef Instance; /!< Register base address */
357	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
358	HAL_TIM_ActiveChannel Channel; /!< Active channel /
359	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
360	This array is accessed by a @ref DMA_Handle_index */
361	HAL_LockTypeDef Lock; /!< Locking object /
362	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
363	__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /!< TIM channel operation state /
364	__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /!< TIM complementary channel operation state /
365	__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /!< DMA burst operation state /
366
367	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
368	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
369	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
370	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
371	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
372	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
373	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
374	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
375	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
376	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
377	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
378	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
379	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
380	void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp Init Callback */
381	void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp DeInit Callback */
382	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
383	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
384	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
385	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
386	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
387	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
388	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
389	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
390	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
391	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
392	void (* CommutationCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation Callback */
393	void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation half complete Callback */
394	void (* BreakCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Break Callback */
395	void (* Break2Callback)(struct __TIM_HandleTypeDef htim); /!< TIM Break2 Callback */
396	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
397	} TIM_HandleTypeDef;
398
399	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
400	/**
401	* @brief HAL TIM Callback ID enumeration definition
402	*/
403	typedef enum
404	{
405	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
406	, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
407	, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
408	, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
409	, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
410	, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
411	, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
412	, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
413	, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
414	, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
415	, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
416	, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
417	, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /!< TIM Hall Sensor MspDeInit Callback ID /
418	, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /!< TIM Hall Sensor MspDeInit Callback ID /
419	, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
420	, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
421	, HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
422	, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
423	, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
424	, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
425	, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
426	, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
427	, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
428	, HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
429	, HAL_TIM_COMMUTATION_CB_ID = 0x18U /!< TIM Commutation Callback ID /
430	, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /!< TIM Commutation half complete Callback ID /
431	, HAL_TIM_BREAK_CB_ID = 0x1AU /!< TIM Break Callback ID /
432	, HAL_TIM_BREAK2_CB_ID = 0x1BU /!< TIM Break2 Callback ID /
433	} HAL_TIM_CallbackIDTypeDef;
434
435	/**
436	* @brief HAL TIM Callback pointer definition
437	*/
438	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
439
440	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
441
442	/**
443	* @}
444	*/
445	/* End of exported types -----------------------------------------------------*/
446
447	/* Exported constants --------------------------------------------------------*/
448	/** @defgroup TIM_Exported_Constants TIM Exported Constants
449	* @{
450	*/
451
452	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
453	* @{
454	*/
455	#define TIM_CLEARINPUTSOURCE_NONE 0x10000000U /!< OCREF_CLR is disabled /
456	#define TIM_CLEARINPUTSOURCE_ETR 0x20000000U /!< OCREF_CLR is connected to ETRF input /
457	#if defined(COMP1) && defined(COMP2) && defined(COMP3)
458	#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /!< OCREF_CLR_INT is connected to COMP1 output /
459	#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0 /!< OCREF_CLR_INT is connected to COMP2 output /
460	#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1 /!< OCREF_CLR_INT is connected to COMP3 output /
461	#elif defined(COMP1) && defined(COMP2)
462	#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /!< OCREF_CLR_INT is connected to COMP1 output /
463	#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR /!< OCREF_CLR_INT is connected to COMP2 output /
464	#endif /* COMP1 && COMP2 && COMP3 */
465	/**
466	* @}
467	*/
468
469	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
470	* @{
471	*/
472	#define TIM_DMABASE_CR1 0x00000000U
473	#define TIM_DMABASE_CR2 0x00000001U
474	#define TIM_DMABASE_SMCR 0x00000002U
475	#define TIM_DMABASE_DIER 0x00000003U
476	#define TIM_DMABASE_SR 0x00000004U
477	#define TIM_DMABASE_EGR 0x00000005U
478	#define TIM_DMABASE_CCMR1 0x00000006U
479	#define TIM_DMABASE_CCMR2 0x00000007U
480	#define TIM_DMABASE_CCER 0x00000008U
481	#define TIM_DMABASE_CNT 0x00000009U
482	#define TIM_DMABASE_PSC 0x0000000AU
483	#define TIM_DMABASE_ARR 0x0000000BU
484	#define TIM_DMABASE_RCR 0x0000000CU
485	#define TIM_DMABASE_CCR1 0x0000000DU
486	#define TIM_DMABASE_CCR2 0x0000000EU
487	#define TIM_DMABASE_CCR3 0x0000000FU
488	#define TIM_DMABASE_CCR4 0x00000010U
489	#define TIM_DMABASE_BDTR 0x00000011U
490	#define TIM_DMABASE_DCR 0x00000012U
491	#define TIM_DMABASE_DMAR 0x00000013U
492	#define TIM_DMABASE_OR1 0x00000014U
493	#define TIM_DMABASE_CCMR3 0x00000015U
494	#define TIM_DMABASE_CCR5 0x00000016U
495	#define TIM_DMABASE_CCR6 0x00000017U
496	#define TIM_DMABASE_AF1 0x00000018U
497	#define TIM_DMABASE_AF2 0x00000019U
498	#define TIM_DMABASE_TISEL 0x0000001AU
499	/**
500	* @}
501	*/
502
503	/** @defgroup TIM_Event_Source TIM Event Source
504	* @{
505	*/
506	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
507	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
508	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
509	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
510	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
511	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
512	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
513	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
514	#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /!< A break 2 event is generated /
515	/**
516	* @}
517	*/
518
519	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
520	* @{
521	*/
522	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
523	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
524	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
525	/**
526	* @}
527	*/
528
529	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
530	* @{
531	*/
532	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
533	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
534	/**
535	* @}
536	*/
537
538	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
539	* @{
540	*/
541	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
542	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
543	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
544	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
545	/**
546	* @}
547	*/
548
549	/** @defgroup TIM_Counter_Mode TIM Counter Mode
550	* @{
551	*/
552	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
553	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
554	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
555	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
556	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
557	/**
558	* @}
559	*/
560
561	/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
562	* @{
563	*/
564	#define TIM_UIFREMAP_DISABLE 0x00000000U /!< Update interrupt flag remap disabled /
565	#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /!< Update interrupt flag remap enabled /
566	/**
567	* @}
568	*/
569
570	/** @defgroup TIM_ClockDivision TIM Clock Division
571	* @{
572	*/
573	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
574	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
575	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
576	/**
577	* @}
578	*/
579
580	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
581	* @{
582	*/
583	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
584	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
585	/**
586	* @}
587	*/
588
589	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
590	* @{
591	*/
592	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
593	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
594
595	/**
596	* @}
597	*/
598
599	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
600	* @{
601	*/
602	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
603	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
604	/**
605	* @}
606	*/
607
608	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
609	* @{
610	*/
611	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
612	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
613	/**
614	* @}
615	*/
616
617	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
618	* @{
619	*/
620	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
621	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
622	/**
623	* @}
624	*/
625
626	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
627	* @{
628	*/
629	#define TIM_OCNPOLARITY_HIGH 0x00000000U /!< Capture/Compare complementary output polarity /
630	#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /!< Capture/Compare complementary output polarity /
631	/**
632	* @}
633	*/
634
635	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
636	* @{
637	*/
638	#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /!< Output Idle state: OCx=1 when MOE=0 /
639	#define TIM_OCIDLESTATE_RESET 0x00000000U /!< Output Idle state: OCx=0 when MOE=0 /
640	/**
641	* @}
642	*/
643
644	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
645	* @{
646	*/
647	#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /!< Complementary output Idle state: OCxN=1 when MOE=0 /
648	#define TIM_OCNIDLESTATE_RESET 0x00000000U /!< Complementary output Idle state: OCxN=0 when MOE=0 /
649	/**
650	* @}
651	*/
652
653	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
654	* @{
655	*/
656	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
657	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
658	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
659	/**
660	* @}
661	*/
662
663	/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
664	* @{
665	*/
666	#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Encoder input with rising edge polarity /
667	#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Encoder input with falling edge polarity /
668	/**
669	* @}
670	*/
671
672	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
673	* @{
674	*/
675	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively /
676	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively /
677	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
678	/**
679	* @}
680	*/
681
682	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
683	* @{
684	*/
685	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
686	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
687	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
688	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
689	/**
690	* @}
691	*/
692
693	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
694	* @{
695	*/
696	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
697	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
698	/**
699	* @}
700	*/
701
702	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
703	* @{
704	*/
705	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
706	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
707	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
708	/**
709	* @}
710	*/
711
712	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
713	* @{
714	*/
715	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
716	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
717	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
718	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
719	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
720	#define TIM_IT_COM TIM_DIER_COMIE /!< Commutation interrupt /
721	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
722	#define TIM_IT_BREAK TIM_DIER_BIE /!< Break interrupt /
723	/**
724	* @}
725	*/
726
727	/** @defgroup TIM_Commutation_Source TIM Commutation Source
728	* @{
729	*/
730	#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input /
731	#define TIM_COMMUTATION_SOFTWARE 0x00000000U /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit /
732	/**
733	* @}
734	*/
735
736	/** @defgroup TIM_DMA_sources TIM DMA Sources
737	* @{
738	*/
739	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
740	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
741	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
742	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
743	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
744	#define TIM_DMA_COM TIM_DIER_COMDE /!< DMA request is triggered by the commutation event /
745	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
746	/**
747	* @}
748	*/
749
750	/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
751	* @{
752	*/
753	#define TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when capture or compare match event occurs /
754	#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
755	/**
756	* @}
757	*/
758
759	/** @defgroup TIM_Flag_definition TIM Flag Definition
760	* @{
761	*/
762	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
763	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
764	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
765	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
766	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
767	#define TIM_FLAG_CC5 TIM_SR_CC5IF /!< Capture/Compare 5 interrupt flag /
768	#define TIM_FLAG_CC6 TIM_SR_CC6IF /!< Capture/Compare 6 interrupt flag /
769	#define TIM_FLAG_COM TIM_SR_COMIF /!< Commutation interrupt flag /
770	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
771	#define TIM_FLAG_BREAK TIM_SR_BIF /!< Break interrupt flag /
772	#define TIM_FLAG_BREAK2 TIM_SR_B2IF /!< Break 2 interrupt flag /
773	#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /!< System Break interrupt flag /
774	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
775	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
776	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
777	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
778	/**
779	* @}
780	*/
781
782	/** @defgroup TIM_Channel TIM Channel
783	* @{
784	*/
785	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
786	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
787	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
788	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
789	#define TIM_CHANNEL_5 0x00000010U /!< Compare channel 5 identifier /
790	#define TIM_CHANNEL_6 0x00000014U /!< Compare channel 6 identifier /
791	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
792	/**
793	* @}
794	*/
795
796	/** @defgroup TIM_Clock_Source TIM Clock Source
797	* @{
798	*/
799	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
800	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
801	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
802	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
803	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
804	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
805	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
806	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
807	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
808	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
809	#if defined(USB_BASE)
810	#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /!< External clock source mode 1 (ITR7) /
811	#endif /* USB_BASE */
812	/**
813	* @}
814	*/
815
816	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
817	* @{
818	*/
819	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
820	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
821	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
822	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
823	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
824	/**
825	* @}
826	*/
827
828	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
829	* @{
830	*/
831	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
832	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
833	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
834	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
835	/**
836	* @}
837	*/
838
839	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
840	* @{
841	*/
842	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
843	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
844	/**
845	* @}
846	*/
847
848	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
849	* @{
850	*/
851	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
852	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
853	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
854	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
855	/**
856	* @}
857	*/
858
859	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
860	* @{
861	*/
862	#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
863	#define TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
864	/**
865	* @}
866	*/
867
868	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
869	* @{
870	*/
871	#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
872	#define TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
873	/**
874	* @}
875	*/
876	/** @defgroup TIM_Lock_level TIM Lock level
877	* @{
878	*/
879	#define TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF /
880	#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
881	#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
882	#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
883	/**
884	* @}
885	*/
886
887	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
888	* @{
889	*/
890	#define TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break input BRK is enabled /
891	#define TIM_BREAK_DISABLE 0x00000000U /!< Break input BRK is disabled /
892	/**
893	* @}
894	*/
895
896	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
897	* @{
898	*/
899	#define TIM_BREAKPOLARITY_LOW 0x00000000U /!< Break input BRK is active low /
900	#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
901	/**
902	* @}
903	*/
904
905	/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
906	* @{
907	*/
908	#define TIM_BREAK_AFMODE_INPUT 0x00000000U /!< Break input BRK in input mode /
909	#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /!< Break input BRK in bidirectional mode /
910	/**
911	* @}
912	*/
913
914	/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
915	* @{
916	*/
917	#define TIM_BREAK2_DISABLE 0x00000000U /!< Break input BRK2 is disabled /
918	#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break input BRK2 is enabled /
919	/**
920	* @}
921	*/
922
923	/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
924	* @{
925	*/
926	#define TIM_BREAK2POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
927	#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
928	/**
929	* @}
930	*/
931
932	/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
933	* @{
934	*/
935	#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /!< Break2 input BRK2 in input mode /
936	#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /!< Break2 input BRK2 in bidirectional mode /
937	/**
938	* @}
939	*/
940
941	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
942	* @{
943	*/
944	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
945	#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) /
946	/**
947	* @}
948	*/
949
950	/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
951	* @{
952	*/
953	#define TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
954	#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
955	#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
956	#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
957	/**
958	* @}
959	*/
960
961	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
962	* @{
963	*/
964	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
965	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
966	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
967	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
968	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
969	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
970	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
971	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
972	/**
973	* @}
974	*/
975
976	/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
977	* @{
978	*/
979	#define TIM_TRGO2_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO2) /
980	#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) /
981	#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output (TRGO2) /
982	#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< Capture or a compare match 1 is used as trigger output (TRGO2) /
983	#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output (TRGO2) /
984	#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output (TRGO2) /
985	#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output (TRGO2) /
986	#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output (TRGO2) /
987	#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output (TRGO2) /
988	#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output (TRGO2) /
989	#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges generate pulses on TRGO2 /
990	#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges generate pulses on TRGO2 /
991	#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges generate pulses on TRGO2 /
992	#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 /
993	#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges generate pulses on TRGO2 /
994	#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF or OC6REF rising edges generate pulses on TRGO2 /
995	/**
996	* @}
997	*/
998
999	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
1000	* @{
1001	*/
1002	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
1003	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
1004	/**
1005	* @}
1006	*/
1007
1008	/** @defgroup TIM_Slave_Mode TIM Slave mode
1009	* @{
1010	*/
1011	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
1012	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
1013	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
1014	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
1015	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
1016	#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode /
1017	/**
1018	* @}
1019	*/
1020
1021	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
1022	* @{
1023	*/
1024	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
1025	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
1026	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
1027	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
1028	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
1029	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
1030	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
1031	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
1032	#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /!< Retrigerrable OPM mode 1 /
1033	#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!< Retrigerrable OPM mode 2 /
1034	#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!< Combined PWM mode 1 /
1035	#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!< Combined PWM mode 2 /
1036	#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!< Asymmetric PWM mode 1 /
1037	#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /!< Asymmetric PWM mode 2 /
1038	/**
1039	* @}
1040	*/
1041
1042	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1043	* @{
1044	*/
1045	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
1046	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
1047	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
1048	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
1049	#if defined(USB_BASE)
1050	#define TIM_TS_ITR7 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_3) /!< Internal Trigger 7 (ITR7) /
1051	#endif /* USB_BASE */
1052	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
1053	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
1054	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
1055	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
1056	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
1057	/**
1058	* @}
1059	*/
1060
1061	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1062	* @{
1063	*/
1064	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
1065	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
1066	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
1067	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
1068	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
1069	/**
1070	* @}
1071	*/
1072
1073	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1074	* @{
1075	*/
1076	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
1077	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
1078	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
1079	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
1080	/**
1081	* @}
1082	*/
1083
1084	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1085	* @{
1086	*/
1087	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
1088	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
1089	/**
1090	* @}
1091	*/
1092
1093	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1094	* @{
1095	*/
1096	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA /
1097	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1098	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1099	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1100	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1101	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1102	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1103	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1104	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1105	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1106	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1107	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1108	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1109	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1110	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1111	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1112	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1113	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
1114	/**
1115	* @}
1116	*/
1117
1118	/** @defgroup DMA_Handle_index TIM DMA Handle Index
1119	* @{
1120	*/
1121	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
1122	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
1123	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
1124	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
1125	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
1126	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
1127	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
1128	/**
1129	* @}
1130	*/
1131
1132	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1133	* @{
1134	*/
1135	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
1136	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
1137	#define TIM_CCxN_ENABLE 0x00000004U /!< Complementary output channel is enabled /
1138	#define TIM_CCxN_DISABLE 0x00000000U /!< Complementary output channel is enabled /
1139	/**
1140	* @}
1141	*/
1142
1143	/** @defgroup TIM_Break_System TIM Break System
1144	* @{
1145	*/
1146	#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 /
1147	#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface /
1148	#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 /
1149	#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 /
1150	/**
1151	* @}
1152	*/
1153
1154	/**
1155	* @}
1156	*/
1157	/* End of exported constants -------------------------------------------------*/
1158
1159	/* Exported macros -----------------------------------------------------------*/
1160	/** @defgroup TIM_Exported_Macros TIM Exported Macros
1161	* @{
1162	*/
1163
1164	/** @brief Reset TIM handle state.
1165	* @param __HANDLE__ TIM handle.
1166	* @retval None
1167	*/
1168	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1169	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1170	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1171	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1172	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1173	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1174	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1175	(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1176	(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1177	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1178	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1179	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1180	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1181	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1182	(__HANDLE__)->Base_MspInitCallback = NULL; \
1183	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
1184	(__HANDLE__)->IC_MspInitCallback = NULL; \
1185	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
1186	(__HANDLE__)->OC_MspInitCallback = NULL; \
1187	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
1188	(__HANDLE__)->PWM_MspInitCallback = NULL; \
1189	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1190	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1191	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1192	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
1193	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1194	(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1195	(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1196	} while(0)
1197	#else
1198	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1199	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1200	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1201	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1202	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1203	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1204	(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
1205	(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
1206	(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1207	(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1208	(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1209	(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1210	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1211	} while(0)
1212	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1213
1214	/**
1215	* @brief Enable the TIM peripheral.
1216	* @param __HANDLE__ TIM handle
1217	* @retval None
1218	*/
1219	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
1220
1221	/**
1222	* @brief Enable the TIM main Output.
1223	* @param __HANDLE__ TIM handle
1224	* @retval None
1225	*/
1226	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
1227
1228	/**
1229	* @brief Disable the TIM peripheral.
1230	* @param __HANDLE__ TIM handle
1231	* @retval None
1232	*/
1233	#define __HAL_TIM_DISABLE(__HANDLE__) \
1234	do { \
1235	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1236	{ \
1237	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1238	{ \
1239	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1240	} \
1241	} \
1242	} while(0)
1243
1244	/**
1245	* @brief Disable the TIM main Output.
1246	* @param __HANDLE__ TIM handle
1247	* @retval None
1248	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
1249	* disabled
1250	*/
1251	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1252	do { \
1253	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1254	{ \
1255	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1256	{ \
1257	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1258	} \
1259	} \
1260	} while(0)
1261
1262	/**
1263	* @brief Disable the TIM main Output.
1264	* @param __HANDLE__ TIM handle
1265	* @retval None
1266	* @note The Main Output Enable of a timer instance is disabled unconditionally
1267	*/
1268	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1269
1270	/** @brief Enable the specified TIM interrupt.
1271	* @param __HANDLE__ specifies the TIM Handle.
1272	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
1273	* This parameter can be one of the following values:
1274	* @arg TIM_IT_UPDATE: Update interrupt
1275	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1276	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1277	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1278	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1279	* @arg TIM_IT_COM: Commutation interrupt
1280	* @arg TIM_IT_TRIGGER: Trigger interrupt
1281	* @arg TIM_IT_BREAK: Break interrupt
1282	* @retval None
1283	*/
1284	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
1285
1286	/** @brief Disable the specified TIM interrupt.
1287	* @param __HANDLE__ specifies the TIM Handle.
1288	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
1289	* This parameter can be one of the following values:
1290	* @arg TIM_IT_UPDATE: Update interrupt
1291	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1292	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1293	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1294	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1295	* @arg TIM_IT_COM: Commutation interrupt
1296	* @arg TIM_IT_TRIGGER: Trigger interrupt
1297	* @arg TIM_IT_BREAK: Break interrupt
1298	* @retval None
1299	*/
1300	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1301
1302	/** @brief Enable the specified DMA request.
1303	* @param __HANDLE__ specifies the TIM Handle.
1304	* @param __DMA__ specifies the TIM DMA request to enable.
1305	* This parameter can be one of the following values:
1306	* @arg TIM_DMA_UPDATE: Update DMA request
1307	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1308	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1309	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1310	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1311	* @arg TIM_DMA_COM: Commutation DMA request
1312	* @arg TIM_DMA_TRIGGER: Trigger DMA request
1313	* @retval None
1314	*/
1315	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
1316
1317	/** @brief Disable the specified DMA request.
1318	* @param __HANDLE__ specifies the TIM Handle.
1319	* @param __DMA__ specifies the TIM DMA request to disable.
1320	* This parameter can be one of the following values:
1321	* @arg TIM_DMA_UPDATE: Update DMA request
1322	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1323	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1324	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1325	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1326	* @arg TIM_DMA_COM: Commutation DMA request
1327	* @arg TIM_DMA_TRIGGER: Trigger DMA request
1328	* @retval None
1329	*/
1330	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1331
1332	/** @brief Check whether the specified TIM interrupt flag is set or not.
1333	* @param __HANDLE__ specifies the TIM Handle.
1334	* @param __FLAG__ specifies the TIM interrupt flag to check.
1335	* This parameter can be one of the following values:
1336	* @arg TIM_FLAG_UPDATE: Update interrupt flag
1337	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1338	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1339	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1340	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1341	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1342	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1343	* @arg TIM_FLAG_COM: Commutation interrupt flag
1344	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1345	* @arg TIM_FLAG_BREAK: Break interrupt flag
1346	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1347	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1348	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1349	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1350	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1351	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1352	* @retval The new state of __FLAG__ (TRUE or FALSE).
1353	*/
1354	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1355
1356	/** @brief Clear the specified TIM interrupt flag.
1357	* @param __HANDLE__ specifies the TIM Handle.
1358	* @param __FLAG__ specifies the TIM interrupt flag to clear.
1359	* This parameter can be one of the following values:
1360	* @arg TIM_FLAG_UPDATE: Update interrupt flag
1361	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1362	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1363	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1364	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1365	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1366	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1367	* @arg TIM_FLAG_COM: Commutation interrupt flag
1368	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1369	* @arg TIM_FLAG_BREAK: Break interrupt flag
1370	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1371	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1372	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1373	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1374	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1375	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1376	* @retval The new state of __FLAG__ (TRUE or FALSE).
1377	*/
1378	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1379
1380	/**
1381	* @brief Check whether the specified TIM interrupt source is enabled or not.
1382	* @param __HANDLE__ TIM handle
1383	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
1384	* This parameter can be one of the following values:
1385	* @arg TIM_IT_UPDATE: Update interrupt
1386	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1387	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1388	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1389	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1390	* @arg TIM_IT_COM: Commutation interrupt
1391	* @arg TIM_IT_TRIGGER: Trigger interrupt
1392	* @arg TIM_IT_BREAK: Break interrupt
1393	* @retval The state of TIM_IT (SET or RESET).
1394	*/
1395	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1396	== (__INTERRUPT__)) ? SET : RESET)
1397
1398	/** @brief Clear the TIM interrupt pending bits.
1399	* @param __HANDLE__ TIM handle
1400	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1401	* This parameter can be one of the following values:
1402	* @arg TIM_IT_UPDATE: Update interrupt
1403	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1404	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1405	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1406	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1407	* @arg TIM_IT_COM: Commutation interrupt
1408	* @arg TIM_IT_TRIGGER: Trigger interrupt
1409	* @arg TIM_IT_BREAK: Break interrupt
1410	* @retval None
1411	*/
1412	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1413
1414	/**
1415	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1416	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1417	* in an atomic way.
1418	* @param __HANDLE__ TIM handle.
1419	* @retval None
1420	mode.
1421	*/
1422	#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 \|= TIM_CR1_UIFREMAP))
1423
1424	/**
1425	* @brief Disable update interrupt flag (UIF) remapping.
1426	* @param __HANDLE__ TIM handle.
1427	* @retval None
1428	mode.
1429	*/
1430	#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1431
1432	/**
1433	* @brief Get update interrupt flag (UIF) copy status.
1434	* @param __COUNTER__ Counter value.
1435	* @retval The state of UIFCPY (TRUE or FALSE).
1436	mode.
1437	*/
1438	#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1439
1440	/**
1441	* @brief Indicates whether or not the TIM Counter is used as downcounter.
1442	* @param __HANDLE__ TIM handle.
1443	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1444	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
1445	* or Encoder mode.
1446	*/
1447	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1448
1449	/**
1450	* @brief Set the TIM Prescaler on runtime.
1451	* @param __HANDLE__ TIM handle.
1452	* @param __PRESC__ specifies the Prescaler new value.
1453	* @retval None
1454	*/
1455	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1456
1457	/**
1458	* @brief Set the TIM Counter Register value on runtime.
1459	* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
1460	* case of 32 bits counter TIM instance.
1461	* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
1462	* @param __HANDLE__ TIM handle.
1463	* @param __COUNTER__ specifies the Counter register new value.
1464	* @retval None
1465	*/
1466	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1467
1468	/**
1469	* @brief Get the TIM Counter Register value on runtime.
1470	* @param __HANDLE__ TIM handle.
1471	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1472	*/
1473	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1474
1475	/**
1476	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1477	* @param __HANDLE__ TIM handle.
1478	* @param __AUTORELOAD__ specifies the Counter register new value.
1479	* @retval None
1480	*/
1481	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1482	do{ \
1483	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1484	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1485	} while(0)
1486
1487	/**
1488	* @brief Get the TIM Autoreload Register value on runtime.
1489	* @param __HANDLE__ TIM handle.
1490	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1491	*/
1492	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1493
1494	/**
1495	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1496	* @param __HANDLE__ TIM handle.
1497	* @param __CKD__ specifies the clock division value.
1498	* This parameter can be one of the following value:
1499	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1500	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1501	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1502	* @retval None
1503	*/
1504	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1505	do{ \
1506	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1507	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
1508	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
1509	} while(0)
1510
1511	/**
1512	* @brief Get the TIM Clock Division value on runtime.
1513	* @param __HANDLE__ TIM handle.
1514	* @retval The clock division can be one of the following values:
1515	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1516	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1517	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1518	*/
1519	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1520
1521	/**
1522	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
1523	* function.
1524	* @param __HANDLE__ TIM handle.
1525	* @param __CHANNEL__ TIM Channels to be configured.
1526	* This parameter can be one of the following values:
1527	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1528	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1529	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1530	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1531	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1532	* This parameter can be one of the following values:
1533	* @arg TIM_ICPSC_DIV1: no prescaler
1534	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1535	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1536	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1537	* @retval None
1538	*/
1539	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1540	do{ \
1541	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1542	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1543	} while(0)
1544
1545	/**
1546	* @brief Get the TIM Input Capture prescaler on runtime.
1547	* @param __HANDLE__ TIM handle.
1548	* @param __CHANNEL__ TIM Channels to be configured.
1549	* This parameter can be one of the following values:
1550	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1551	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1552	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1553	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1554	* @retval The input capture prescaler can be one of the following values:
1555	* @arg TIM_ICPSC_DIV1: no prescaler
1556	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1557	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1558	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1559	*/
1560	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1561	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1562	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1563	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1564	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1565
1566	/**
1567	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1568	* @param __HANDLE__ TIM handle.
1569	* @param __CHANNEL__ TIM Channels to be configured.
1570	* This parameter can be one of the following values:
1571	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1572	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1573	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1574	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1575	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
1576	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
1577	* @param __COMPARE__ specifies the Capture Compare register new value.
1578	* @retval None
1579	*/
1580	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1581	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1582	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1583	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1584	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1585	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1586	((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1587
1588	/**
1589	* @brief Get the TIM Capture Compare Register value on runtime.
1590	* @param __HANDLE__ TIM handle.
1591	* @param __CHANNEL__ TIM Channel associated with the capture compare register
1592	* This parameter can be one of the following values:
1593	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
1594	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
1595	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
1596	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
1597	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
1598	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
1599	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1600	*/
1601	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1602	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1603	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1604	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1605	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1606	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1607	((__HANDLE__)->Instance->CCR6))
1608
1609	/**
1610	* @brief Set the TIM Output compare preload.
1611	* @param __HANDLE__ TIM handle.
1612	* @param __CHANNEL__ TIM Channels to be configured.
1613	* This parameter can be one of the following values:
1614	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1615	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1616	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1617	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1618	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
1619	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
1620	* @retval None
1621	*/
1622	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1623	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
1624	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
1625	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
1626	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE) :\
1627	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC5PE) :\
1628	((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC6PE))
1629
1630	/**
1631	* @brief Reset the TIM Output compare preload.
1632	* @param __HANDLE__ TIM handle.
1633	* @param __CHANNEL__ TIM Channels to be configured.
1634	* This parameter can be one of the following values:
1635	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1636	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1637	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1638	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1639	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
1640	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
1641	* @retval None
1642	*/
1643	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1644	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1645	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1646	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1647	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1648	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1649	((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1650
1651	/**
1652	* @brief Enable fast mode for a given channel.
1653	* @param __HANDLE__ TIM handle.
1654	* @param __CHANNEL__ TIM Channels to be configured.
1655	* This parameter can be one of the following values:
1656	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1657	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1658	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1659	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1660	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
1661	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
1662	* @note When fast mode is enabled an active edge on the trigger input acts
1663	* like a compare match on CCx output. Delay to sample the trigger
1664	* input and to activate CCx output is reduced to 3 clock cycles.
1665	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
1666	* @retval None
1667	*/
1668	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1669	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
1670	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
1671	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
1672	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE) :\
1673	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC5FE) :\
1674	((__HANDLE__)->Instance->CCMR3 \|= TIM_CCMR3_OC6FE))
1675
1676	/**
1677	* @brief Disable fast mode for a given channel.
1678	* @param __HANDLE__ TIM handle.
1679	* @param __CHANNEL__ TIM Channels to be configured.
1680	* This parameter can be one of the following values:
1681	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1682	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1683	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1684	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1685	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
1686	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
1687	* @note When fast mode is disabled CCx output behaves normally depending
1688	* on counter and CCRx values even when the trigger is ON. The minimum
1689	* delay to activate CCx output when an active edge occurs on the
1690	* trigger input is 5 clock cycles.
1691	* @retval None
1692	*/
1693	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1694	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1695	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1696	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1697	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1698	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1699	((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1700
1701	/**
1702	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1703	* @param __HANDLE__ TIM handle.
1704	* @note When the URS bit of the TIMx_CR1 register is set, only counter
1705	* overflow/underflow generates an update interrupt or DMA request (if
1706	* enabled)
1707	* @retval None
1708	*/
1709	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
1710
1711	/**
1712	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1713	* @param __HANDLE__ TIM handle.
1714	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
1715	* following events generate an update interrupt or DMA request (if
1716	* enabled):
1717	* _ Counter overflow underflow
1718	* _ Setting the UG bit
1719	* _ Update generation through the slave mode controller
1720	* @retval None
1721	*/
1722	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1723
1724	/**
1725	* @brief Set the TIM Capture x input polarity on runtime.
1726	* @param __HANDLE__ TIM handle.
1727	* @param __CHANNEL__ TIM Channels to be configured.
1728	* This parameter can be one of the following values:
1729	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
1730	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
1731	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
1732	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
1733	* @param __POLARITY__ Polarity for TIx source
1734	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1735	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1736	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1737	* @retval None
1738	*/
1739	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1740	do{ \
1741	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1742	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1743	}while(0)
1744
1745	/** @brief Select the Capture/compare DMA request source.
1746	* @param __HANDLE__ specifies the TIM Handle.
1747	* @param __CCDMA__ specifies Capture/compare DMA request source
1748	* This parameter can be one of the following values:
1749	* @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
1750	* @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
1751	* @retval None
1752	*/
1753	#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
1754	MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
1755
1756	/**
1757	* @}
1758	*/
1759	/* End of exported macros ----------------------------------------------------*/
1760
1761	/* Private constants ---------------------------------------------------------*/
1762	/** @defgroup TIM_Private_Constants TIM Private Constants
1763	* @{
1764	*/
1765	/* The counter of a timer instance is disabled only if all the CCx and CCxN
1766	channels have been disabled */
1767	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
1768	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
1769	/**
1770	* @}
1771	*/
1772	/* End of private constants --------------------------------------------------*/
1773
1774	/* Private macros ------------------------------------------------------------*/
1775	/** @defgroup TIM_Private_Macros TIM Private Macros
1776	* @{
1777	*/
1778	#if defined(COMP1) && defined(COMP2) && defined(COMP3)
1779	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
1780	((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) \|\| \
1781	((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) \|\| \
1782	((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) \|\| \
1783	((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1784	#elif defined(COMP1) && defined(COMP2)
1785	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
1786	((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) \|\| \
1787	((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) \|\| \
1788	((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1789	#else
1790	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
1791	((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1792	#endif /* COMP1 && COMP2 && COMP3 */
1793
1794	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
1795	((__BASE__) == TIM_DMABASE_CR2) \|\| \
1796	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
1797	((__BASE__) == TIM_DMABASE_DIER) \|\| \
1798	((__BASE__) == TIM_DMABASE_SR) \|\| \
1799	((__BASE__) == TIM_DMABASE_EGR) \|\| \
1800	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
1801	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
1802	((__BASE__) == TIM_DMABASE_CCER) \|\| \
1803	((__BASE__) == TIM_DMABASE_CNT) \|\| \
1804	((__BASE__) == TIM_DMABASE_PSC) \|\| \
1805	((__BASE__) == TIM_DMABASE_ARR) \|\| \
1806	((__BASE__) == TIM_DMABASE_RCR) \|\| \
1807	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
1808	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
1809	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
1810	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
1811	((__BASE__) == TIM_DMABASE_BDTR) \|\| \
1812	((__BASE__) == TIM_DMABASE_OR1) \|\| \
1813	((__BASE__) == TIM_DMABASE_CCMR3) \|\| \
1814	((__BASE__) == TIM_DMABASE_CCR5) \|\| \
1815	((__BASE__) == TIM_DMABASE_CCR6) \|\| \
1816	((__BASE__) == TIM_DMABASE_AF1) \|\| \
1817	((__BASE__) == TIM_DMABASE_AF2) \|\| \
1818	((__BASE__) == TIM_DMABASE_TISEL))
1819
1820	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1821
1822	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
1823	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
1824	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
1825	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
1826	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1827
1828	#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) \|\| \
1829	((__MODE__) == TIM_UIFREMAP_ENABLE))
1830
1831	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
1832	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
1833	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1834
1835	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
1836	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1837
1838	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
1839	((__STATE__) == TIM_OCFAST_ENABLE))
1840
1841	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
1842	((__POLARITY__) == TIM_OCPOLARITY_LOW))
1843
1844	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
1845	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1846
1847	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
1848	((__STATE__) == TIM_OCIDLESTATE_RESET))
1849
1850	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
1851	((__STATE__) == TIM_OCNIDLESTATE_RESET))
1852
1853	#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) \|\| \
1854	((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1855
1856	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
1857	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
1858	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1859
1860	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
1861	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
1862	((__SELECTION__) == TIM_ICSELECTION_TRC))
1863
1864	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
1865	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
1866	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
1867	((__PRESCALER__) == TIM_ICPSC_DIV8))
1868
1869	#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
1870	((__CHANNEL__) != (TIM_CHANNEL_5)) && \
1871	((__CHANNEL__) != (TIM_CHANNEL_6)))
1872
1873	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
1874	((__MODE__) == TIM_OPMODE_REPETITIVE))
1875
1876	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
1877	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
1878	((__MODE__) == TIM_ENCODERMODE_TI12))
1879
1880	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1881
1882	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
1883	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
1884	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
1885	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
1886	((__CHANNEL__) == TIM_CHANNEL_5) \|\| \
1887	((__CHANNEL__) == TIM_CHANNEL_6) \|\| \
1888	((__CHANNEL__) == TIM_CHANNEL_ALL))
1889
1890	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
1891	((__CHANNEL__) == TIM_CHANNEL_2))
1892
1893	#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
1894	(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
1895	((__PERIOD__) > 0U))
1896
1897	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
1898	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
1899	((__CHANNEL__) == TIM_CHANNEL_3))
1900
1901	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
1902	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) \|\| \
1903	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
1904	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
1905	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
1906	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
1907	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
1908	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
1909	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
1910	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
1911
1912	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
1913	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
1914	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
1915	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
1916	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1917
1918	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
1919	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
1920	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
1921	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1922
1923	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1924
1925	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
1926	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1927
1928	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
1929	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
1930	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
1931	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1932
1933	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1934
1935	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
1936	((__STATE__) == TIM_OSSR_DISABLE))
1937
1938	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
1939	((__STATE__) == TIM_OSSI_DISABLE))
1940
1941	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
1942	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
1943	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
1944	((__LEVEL__) == TIM_LOCKLEVEL_3))
1945
1946	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1947
1948	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
1949	((__STATE__) == TIM_BREAK_DISABLE))
1950
1951	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
1952	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1953
1954	#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) \|\| \
1955	((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
1956
1957
1958	#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) \|\| \
1959	((__STATE__) == TIM_BREAK2_DISABLE))
1960
1961	#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) \|\| \
1962	((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1963
1964	#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) \|\| \
1965	((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
1966
1967
1968	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
1969	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1970
1971	#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1972
1973	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
1974	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
1975	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
1976	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
1977	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
1978	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
1979	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
1980	((__SOURCE__) == TIM_TRGO_OC4REF))
1981
1982	#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) \|\| \
1983	((__SOURCE__) == TIM_TRGO2_ENABLE) \|\| \
1984	((__SOURCE__) == TIM_TRGO2_UPDATE) \|\| \
1985	((__SOURCE__) == TIM_TRGO2_OC1) \|\| \
1986	((__SOURCE__) == TIM_TRGO2_OC1REF) \|\| \
1987	((__SOURCE__) == TIM_TRGO2_OC2REF) \|\| \
1988	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
1989	((__SOURCE__) == TIM_TRGO2_OC3REF) \|\| \
1990	((__SOURCE__) == TIM_TRGO2_OC4REF) \|\| \
1991	((__SOURCE__) == TIM_TRGO2_OC5REF) \|\| \
1992	((__SOURCE__) == TIM_TRGO2_OC6REF) \|\| \
1993	((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) \|\| \
1994	((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) \|\| \
1995	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) \|\| \
1996	((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) \|\| \
1997	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) \|\| \
1998	((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1999
2000	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
2001	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
2002
2003	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
2004	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
2005	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
2006	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
2007	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) \|\| \
2008	((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2009
2010	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
2011	((__MODE__) == TIM_OCMODE_PWM2) \|\| \
2012	((__MODE__) == TIM_OCMODE_COMBINED_PWM1) \|\| \
2013	((__MODE__) == TIM_OCMODE_COMBINED_PWM2) \|\| \
2014	((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) \|\| \
2015	((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
2016
2017	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
2018	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
2019	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
2020	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
2021	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
2022	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) \|\| \
2023	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) \|\| \
2024	((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
2025
2026	#if defined(USB_BASE)
2027	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
2028	((__SELECTION__) == TIM_TS_ITR1) \|\| \
2029	((__SELECTION__) == TIM_TS_ITR2) \|\| \
2030	((__SELECTION__) == TIM_TS_ITR3) \|\| \
2031	((__SELECTION__) == TIM_TS_ITR7) \|\| \
2032	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
2033	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
2034	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
2035	((__SELECTION__) == TIM_TS_ETRF))
2036	#else
2037	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
2038	((__SELECTION__) == TIM_TS_ITR1) \|\| \
2039	((__SELECTION__) == TIM_TS_ITR2) \|\| \
2040	((__SELECTION__) == TIM_TS_ITR3) \|\| \
2041	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
2042	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
2043	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
2044	((__SELECTION__) == TIM_TS_ETRF))
2045	#endif /* USB_BASE */
2046
2047	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
2048	((__SELECTION__) == TIM_TS_ITR1) \|\| \
2049	((__SELECTION__) == TIM_TS_ITR2) \|\| \
2050	((__SELECTION__) == TIM_TS_ITR3) \|\| \
2051	((__SELECTION__) == TIM_TS_NONE))
2052
2053	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
2054	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
2055	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
2056	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
2057	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
2058
2059	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
2060	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
2061	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
2062	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
2063
2064	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2065
2066	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
2067	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2068
2069	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
2070	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
2071	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
2072	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
2073	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
2074	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
2075	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
2076	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
2077	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
2078	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
2079	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
2080	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
2081	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
2082	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
2083	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
2084	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
2085	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
2086	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2087
2088	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2089
2090	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2091
2092	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
2093
2094	#if defined(PWR_PVD_SUPPORT)
2095	#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) \|\| \
2096	((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) \|\| \
2097	((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) \|\| \
2098	((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2099	#else
2100	#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) \|\| \
2101	((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) \|\| \
2102	((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2103	#endif /* PWR_PVD_SUPPORT */
2104
2105	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) \|\| \
2106	((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2107
2108	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2109	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
2110	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
2111	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
2112	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
2113
2114	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2115	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2116	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2117	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2118	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2119
2120	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2121	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
2122	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
2123	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
2124	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
2125
2126	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2127	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
2128	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
2129	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
2130	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
2131
2132	#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2133	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2134	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2135	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2136	((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2137	((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2138	(__HANDLE__)->ChannelState[5])
2139
2140	#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2141	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2142	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2143	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2144	((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2145	((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2146	((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2147
2148	#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2149	(__HANDLE__)->ChannelState[0] = \
2150	(__CHANNEL_STATE__); \
2151	(__HANDLE__)->ChannelState[1] = \
2152	(__CHANNEL_STATE__); \
2153	(__HANDLE__)->ChannelState[2] = \
2154	(__CHANNEL_STATE__); \
2155	(__HANDLE__)->ChannelState[3] = \
2156	(__CHANNEL_STATE__); \
2157	(__HANDLE__)->ChannelState[4] = \
2158	(__CHANNEL_STATE__); \
2159	(__HANDLE__)->ChannelState[5] = \
2160	(__CHANNEL_STATE__); \
2161	} while(0)
2162
2163	#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2164	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2165	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2166	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2167	(__HANDLE__)->ChannelNState[3])
2168
2169	#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2170	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2171	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2172	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2173	((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2174
2175	#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
2176	(__HANDLE__)->ChannelNState[0] = \
2177	(__CHANNEL_STATE__); \
2178	(__HANDLE__)->ChannelNState[1] = \
2179	(__CHANNEL_STATE__); \
2180	(__HANDLE__)->ChannelNState[2] = \
2181	(__CHANNEL_STATE__); \
2182	(__HANDLE__)->ChannelNState[3] = \
2183	(__CHANNEL_STATE__); \
2184	} while(0)
2185
2186	/**
2187	* @}
2188	*/
2189	/* End of private macros -----------------------------------------------------*/
2190
2191	/* Include TIM HAL Extended module */
2192	#include "stm32g0xx_hal_tim_ex.h"
2193
2194	/* Exported functions --------------------------------------------------------*/
2195	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
2196	* @{
2197	*/
2198
2199	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2200	* @brief Time Base functions
2201	* @{
2202	*/
2203	/* Time Base functions ********************************************************/
2204	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2205	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2206	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2207	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2208	/* Blocking mode: Polling */
2209	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2210	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2211	/* Non-Blocking mode: Interrupt */
2212	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2213	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2214	/* Non-Blocking mode: DMA */
2215	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, const uint32_t pData, uint16_t Length);
2216	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2217	/**
2218	* @}
2219	*/
2220
2221	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2222	* @brief TIM Output Compare functions
2223	* @{
2224	*/
2225	/* Timer Output Compare functions *********************************************/
2226	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2227	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2228	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2229	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2230	/* Blocking mode: Polling */
2231	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2232	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2233	/* Non-Blocking mode: Interrupt */
2234	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2235	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2236	/* Non-Blocking mode: DMA */
2237	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, const uint32_t pData,
2238	uint16_t Length);
2239	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2240	/**
2241	* @}
2242	*/
2243
2244	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2245	* @brief TIM PWM functions
2246	* @{
2247	*/
2248	/* Timer PWM functions ********************************************************/
2249	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2250	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2251	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2252	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2253	/* Blocking mode: Polling */
2254	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2255	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2256	/* Non-Blocking mode: Interrupt */
2257	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2258	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2259	/* Non-Blocking mode: DMA */
2260	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, const uint32_t pData,
2261	uint16_t Length);
2262	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2263	/**
2264	* @}
2265	*/
2266
2267	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2268	* @brief TIM Input Capture functions
2269	* @{
2270	*/
2271	/* Timer Input Capture functions **********************************************/
2272	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2273	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2274	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2275	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2276	/* Blocking mode: Polling */
2277	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2278	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2279	/* Non-Blocking mode: Interrupt */
2280	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2281	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2282	/* Non-Blocking mode: DMA */
2283	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
2284	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2285	/**
2286	* @}
2287	*/
2288
2289	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2290	* @brief TIM One Pulse functions
2291	* @{
2292	*/
2293	/* Timer One Pulse functions **************************************************/
2294	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2295	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2296	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2297	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2298	/* Blocking mode: Polling */
2299	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2300	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2301	/* Non-Blocking mode: Interrupt */
2302	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2303	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2304	/**
2305	* @}
2306	*/
2307
2308	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2309	* @brief TIM Encoder functions
2310	* @{
2311	*/
2312	/* Timer Encoder functions ****************************************************/
2313	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, const TIM_Encoder_InitTypeDef sConfig);
2314	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2315	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2316	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2317	/* Blocking mode: Polling */
2318	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2319	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2320	/* Non-Blocking mode: Interrupt */
2321	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2322	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2323	/* Non-Blocking mode: DMA */
2324	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
2325	uint32_t *pData2, uint16_t Length);
2326	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2327	/**
2328	* @}
2329	*/
2330
2331	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2332	* @brief IRQ handler management
2333	* @{
2334	*/
2335	/* Interrupt Handler functions ***********************************************/
2336	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2337	/**
2338	* @}
2339	*/
2340
2341	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2342	* @brief Peripheral Control functions
2343	* @{
2344	*/
2345	/* Control functions *********************************************************/
2346	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, const TIM_OC_InitTypeDef sConfig,
2347	uint32_t Channel);
2348	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, const TIM_OC_InitTypeDef sConfig,
2349	uint32_t Channel);
2350	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, const TIM_IC_InitTypeDef sConfig,
2351	uint32_t Channel);
2352	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
2353	uint32_t OutputChannel, uint32_t InputChannel);
2354	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2355	const TIM_ClearInputConfigTypeDef *sClearInputConfig,
2356	uint32_t Channel);
2357	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, const TIM_ClockConfigTypeDef sClockSourceConfig);
2358	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2359	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, const TIM_SlaveConfigTypeDef sSlaveConfig);
2360	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, const TIM_SlaveConfigTypeDef sSlaveConfig);
2361	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2362	uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2363	uint32_t BurstLength);
2364	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2365	uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2366	uint32_t BurstLength, uint32_t DataLength);
2367	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2368	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2369	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2370	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2371	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
2372	uint32_t BurstLength, uint32_t DataLength);
2373	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2374	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2375	uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
2376	/**
2377	* @}
2378	*/
2379
2380	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2381	* @brief TIM Callbacks functions
2382	* @{
2383	*/
2384	/* Callback in non blocking modes (Interrupt and DMA) *************************/
2385	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2386	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2387	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2388	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2389	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2390	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2391	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2392	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2393	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2394	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2395
2396	/* Callbacks Register/UnRegister functions ***********************************/
2397	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2398	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2399	pTIM_CallbackTypeDef pCallback);
2400	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2401	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2402
2403	/**
2404	* @}
2405	*/
2406
2407	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2408	* @brief Peripheral State functions
2409	* @{
2410	*/
2411	/* Peripheral State functions ************************************************/
2412	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
2413	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
2414	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
2415	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
2416	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
2417	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
2418
2419	/* Peripheral Channel state functions ************************************************/
2420	HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
2421	HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
2422	HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
2423	/**
2424	* @}
2425	*/
2426
2427	/**
2428	* @}
2429	*/
2430	/* End of exported functions -------------------------------------------------*/
2431
2432	/* Private functions----------------------------------------------------------*/
2433	/** @defgroup TIM_Private_Functions TIM Private Functions
2434	* @{
2435	*/
2436	void TIM_Base_SetConfig(TIM_TypeDef TIMx, const TIM_Base_InitTypeDef Structure);
2437	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2438	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, const TIM_OC_InitTypeDef OC_Config);
2439	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2440	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2441
2442	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2443	void TIM_DMAError(DMA_HandleTypeDef *hdma);
2444	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2445	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2446	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2447
2448	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2449	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2450	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2451
2452	/**
2453	* @}
2454	*/
2455	/* End of private functions --------------------------------------------------*/
2456
2457	/**
2458	* @}
2459	*/
2460
2461	/**
2462	* @}
2463	*/
2464
2465	#ifdef __cplusplus
2466	}
2467	#endif
2468
2469	#endif /* STM32G0xx_HAL_TIM_H */

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h

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