Context Navigation

stm32g0xx_ll_dac.h

Last change on this file was 6, checked in by f.jahn, 3 months ago

File size: 83.2 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_dac.h
4	* @author MCD Application Team
5	* @brief Header file of DAC LL module.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19
20	/* Define to prevent recursive inclusion -------------------------------------*/
21	#ifndef STM32G0xx_LL_DAC_H
22	#define STM32G0xx_LL_DAC_H
23
24	#ifdef __cplusplus
25	extern "C" {
26	#endif
27
28	/* Includes ------------------------------------------------------------------*/
29	#include "stm32g0xx.h"
30
31	/** @addtogroup STM32G0xx_LL_Driver
32	* @{
33	*/
34
35	#if defined(DAC1)
36
37	/** @defgroup DAC_LL DAC
38	* @{
39	*/
40
41	/* Private types -------------------------------------------------------------*/
42	/* Private variables ---------------------------------------------------------*/
43
44	/* Private constants ---------------------------------------------------------*/
45	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
46	* @{
47	*/
48
49	/* Internal masks for DAC channels definition */
50	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51	/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
52	/* - channel bits position into register SWTRIG */
53	/* - channel register offset of data holding register DHRx */
54	/* - channel register offset of data output register DORx */
55	/* - channel register offset of sample-and-hold sample time register SHSRx */
56	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
57	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
58	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
59
60	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
61	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
62	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
63
64	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
65	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
66	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
67	#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
68	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
69	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
70	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
71	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
72	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
73	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
74
75	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
76	#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
77	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
78	#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
79	#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
80	#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_SHSR2_REGOFFSET)
81
82
83	#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
84	#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
85	#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
86
87	#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
88	#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
89	#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
90	#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
91	#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
92
93	/* DAC registers bits positions */
94	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
95	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
96	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
97
98	/* Miscellaneous data */
99	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
100
101	/**
102	* @}
103	*/
104
105
106	/* Private macros ------------------------------------------------------------*/
107	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
108	* @{
109	*/
110
111	/**
112	* @brief Driver macro reserved for internal use: set a pointer to
113	* a register from a register basis from which an offset
114	* is applied.
115	* @param __REG__ Register basis from which the offset is applied.
116	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
117	* @retval Pointer to register address
118	*/
119	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
120	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
121
122	/**
123	* @}
124	*/
125
126
127	/* Exported types ------------------------------------------------------------*/
128	#if defined(USE_FULL_LL_DRIVER)
129	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
130	* @{
131	*/
132
133	/**
134	* @brief Structure definition of some features of DAC instance.
135	*/
136	typedef struct
137	{
138	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
139	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
140
141	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
142
143	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
144	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
145
146	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
147
148	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
149	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
150	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
151	@note If waveform automatic generation mode is disabled, this parameter is discarded.
152
153	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
154	depending on the wave automatic generation selected. */
155
156	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
157	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
158
159	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
160
161
162	uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
163	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
164
165	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
166
167	uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
168	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
169
170	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
171	} LL_DAC_InitTypeDef;
172
173	/**
174	* @}
175	*/
176	#endif /* USE_FULL_LL_DRIVER */
177
178	/* Exported constants --------------------------------------------------------*/
179	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
180	* @{
181	*/
182
183	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
184	* @brief Flags defines which can be used with LL_DAC_ReadReg function
185	* @{
186	*/
187	/* DAC channel 1 flags */
188	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
189	#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /!< DAC channel 1 flag offset calibration status /
190	#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /!< DAC channel 1 flag busy writing sample time /
191
192	/* DAC channel 2 flags */
193	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
194	#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /!< DAC channel 2 flag offset calibration status /
195	#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /!< DAC channel 2 flag busy writing sample time /
196	/**
197	* @}
198	*/
199
200	/** @defgroup DAC_LL_EC_IT DAC interruptions
201	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
202	* @{
203	*/
204	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
205	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
206	/**
207	* @}
208	*/
209
210	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
211	* @{
212	*/
213	#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
214	#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET \| DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
215	/**
216	* @}
217	*/
218
219	/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
220	* @{
221	*/
222	#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /!< DAC channel in mode normal operation /
223	#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /!< DAC channel in mode calibration /
224	/**
225	* @}
226	*/
227
228	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
229	* @{
230	*/
231	#define LL_DAC_TRIG_SOFTWARE 0x00000000U /!< DAC channel conversion trigger internal (SW start) /
232	#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. /
233	#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. /
234	#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. /
235	#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. /
236	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. /
237	#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. /
238	#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. /
239	#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. /
240	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external peripheral: external interrupt line 9. /
241	/**
242	* @}
243	*/
244
245	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
246	* @{
247	*/
248	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
249	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
250	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
251	/**
252	* @}
253	*/
254
255	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
256	* @{
257	*/
258	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
259	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
260	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
261	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
262	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
263	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
264	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
270	/**
271	* @}
272	*/
273
274	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
275	* @{
276	*/
277	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
278	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
279	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
280	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
281	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
282	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
283	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
284	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
285	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
286	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
287	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
288	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
289	/**
290	* @}
291	*/
292
293	/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
294	* @{
295	*/
296	#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /!< The selected DAC channel output is on mode normal. /
297	#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). /
298	/**
299	* @}
300	*/
301
302	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
303	* @{
304	*/
305	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
306	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
307	/**
308	* @}
309	*/
310
311	/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
312	* @{
313	*/
314	#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /!< The selected DAC channel output is connected to external pin /
315	#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). /
316	/**
317	* @}
318	*/
319
320	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
321	* @{
322	*/
323	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
324	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
325	/**
326	* @}
327	*/
328
329	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
330	* @{
331	*/
332	/* List of DAC registers intended to be used (most commonly) with */
333	/* DMA transfer. */
334	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
335	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits right aligned /
336	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits left aligned /
337	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 8 bits right aligned /
338	/**
339	* @}
340	*/
341
342	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
343	* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
344	* not timeout values.
345	* For details on delays values, refer to descriptions in source code
346	* above each literal definition.
347	* @{
348	*/
349
350	/* Delay for DAC channel voltage settling time from DAC channel startup */
351	/* (transition from disable to enable). */
352	/* Note: DAC channel startup time depends on board application environment: */
353	/* impedance connected to DAC channel output. */
354	/* The delay below is specified under conditions: */
355	/* - voltage maximum transition (lowest to highest value) */
356	/* - until voltage reaches final value +-1LSB */
357	/* - DAC channel output buffer enabled */
358	/* - load impedance of 5kOhm (min), 50pF (max) */
359	/* Literal set to maximum value (refer to device datasheet, */
360	/* parameter "tWAKEUP"). */
361	/* Unit: us */
362	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
363
364	/* Delay for DAC channel voltage settling time. */
365	/* Note: DAC channel startup time depends on board application environment: */
366	/* impedance connected to DAC channel output. */
367	/* The delay below is specified under conditions: */
368	/* - voltage maximum transition (lowest to highest value) */
369	/* - until voltage reaches final value +-1LSB */
370	/* - DAC channel output buffer enabled */
371	/* - load impedance of 5kOhm min, 50pF max */
372	/* Literal set to maximum value (refer to device datasheet, */
373	/* parameter "tSETTLING"). */
374	/* Unit: us */
375	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /!< Delay for DAC channel voltage settling time /
376
377	/**
378	* @}
379	*/
380
381	/**
382	* @}
383	*/
384
385	/* Exported macro ------------------------------------------------------------*/
386	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
387	* @{
388	*/
389
390	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
391	* @{
392	*/
393
394	/**
395	* @brief Write a value in DAC register
396	* @param __INSTANCE__ DAC Instance
397	* @param __REG__ Register to be written
398	* @param __VALUE__ Value to be written in the register
399	* @retval None
400	*/
401	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
402
403	/**
404	* @brief Read a value in DAC register
405	* @param __INSTANCE__ DAC Instance
406	* @param __REG__ Register to be read
407	* @retval Register value
408	*/
409	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
410
411	/**
412	* @}
413	*/
414
415	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
416	* @{
417	*/
418
419	/**
420	* @brief Helper macro to get DAC channel number in decimal format
421	* from literals LL_DAC_CHANNEL_x.
422	* Example:
423	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
424	* will return decimal number "1".
425	* @note The input can be a value from functions where a channel
426	* number is returned.
427	* @param __CHANNEL__ This parameter can be one of the following values:
428	* @arg @ref LL_DAC_CHANNEL_1
429	* @arg @ref LL_DAC_CHANNEL_2
430	* @retval 1...2
431	*/
432	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
433	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
434
435	/**
436	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
437	* from number in decimal format.
438	* Example:
439	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
440	* will return a data equivalent to "LL_DAC_CHANNEL_1".
441	* @note If the input parameter does not correspond to a DAC channel,
442	* this macro returns value '0'.
443	* @param __DECIMAL_NB__ 1...2
444	* @retval Returned value can be one of the following values:
445	* @arg @ref LL_DAC_CHANNEL_1
446	* @arg @ref LL_DAC_CHANNEL_2
447	*/
448	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
449	(((__DECIMAL_NB__) == 1U) \
450	? ( \
451	LL_DAC_CHANNEL_1 \
452	) \
453	: \
454	(((__DECIMAL_NB__) == 2U) \
455	? ( \
456	LL_DAC_CHANNEL_2 \
457	) \
458	: \
459	( \
460	0U \
461	) \
462	) \
463	)
464
465	/**
466	* @brief Helper macro to define the DAC conversion data full-scale digital
467	* value corresponding to the selected DAC resolution.
468	* @note DAC conversion data full-scale corresponds to voltage range
469	* determined by analog voltage references Vref+ and Vref-
470	* (refer to reference manual).
471	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
472	* @arg @ref LL_DAC_RESOLUTION_12B
473	* @arg @ref LL_DAC_RESOLUTION_8B
474	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
475	*/
476	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
477	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
478
479	/**
480	* @brief Helper macro to calculate the DAC conversion data (unit: digital
481	* value) corresponding to a voltage (unit: mVolt).
482	* @note This helper macro is intended to provide input data in voltage
483	* rather than digital value,
484	* to be used with LL DAC functions such as
485	* @ref LL_DAC_ConvertData12RightAligned().
486	* @note Analog reference voltage (Vref+) must be either known from
487	* user board environment or can be calculated using ADC measurement
488	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
489	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
490	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
491	* (unit: mVolt).
492	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
493	* @arg @ref LL_DAC_RESOLUTION_12B
494	* @arg @ref LL_DAC_RESOLUTION_8B
495	* @retval DAC conversion data (unit: digital value)
496	*/
497	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
498	__DAC_VOLTAGE__,\
499	__DAC_RESOLUTION__) \
500	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
501	/ (__VREFANALOG_VOLTAGE__) \
502	)
503
504	/**
505	* @}
506	*/
507
508	/**
509	* @}
510	*/
511
512
513	/* Exported functions --------------------------------------------------------*/
514	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
515	* @{
516	*/
517	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
518	* @{
519	*/
520
521	/**
522	* @brief Set the operating mode for the selected DAC channel:
523	* calibration or normal operating mode.
524	* @rmtoll CR CEN1 LL_DAC_SetMode\n
525	* CR CEN2 LL_DAC_SetMode
526	* @param DACx DAC instance
527	* @param DAC_Channel This parameter can be one of the following values:
528	* @arg @ref LL_DAC_CHANNEL_1
529	* @arg @ref LL_DAC_CHANNEL_2
530	* @param ChannelMode This parameter can be one of the following values:
531	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
532	* @arg @ref LL_DAC_MODE_CALIBRATION
533	* @retval None
534	*/
535	__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
536	{
537	MODIFY_REG(DACx->CR,
538	DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
539	ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
540	}
541
542	/**
543	* @brief Get the operating mode for the selected DAC channel:
544	* calibration or normal operating mode.
545	* @rmtoll CR CEN1 LL_DAC_GetMode\n
546	* CR CEN2 LL_DAC_GetMode
547	* @param DACx DAC instance
548	* @param DAC_Channel This parameter can be one of the following values:
549	* @arg @ref LL_DAC_CHANNEL_1
550	* @arg @ref LL_DAC_CHANNEL_2
551	* @retval Returned value can be one of the following values:
552	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
553	* @arg @ref LL_DAC_MODE_CALIBRATION
554	*/
555	__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
556	{
557	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
558	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
559	);
560	}
561
562	/**
563	* @brief Set the offset trimming value for the selected DAC channel.
564	* Trimming has an impact when output buffer is enabled
565	* and is intended to replace factory calibration default values.
566	* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
567	* CCR OTRIM2 LL_DAC_SetTrimmingValue
568	* @param DACx DAC instance
569	* @param DAC_Channel This parameter can be one of the following values:
570	* @arg @ref LL_DAC_CHANNEL_1
571	* @arg @ref LL_DAC_CHANNEL_2
572	* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
573	* @retval None
574	*/
575	__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
576	{
577	MODIFY_REG(DACx->CCR,
578	DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
579	TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
580	}
581
582	/**
583	* @brief Get the offset trimming value for the selected DAC channel.
584	* Trimming has an impact when output buffer is enabled
585	* and is intended to replace factory calibration default values.
586	* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
587	* CCR OTRIM2 LL_DAC_GetTrimmingValue
588	* @param DACx DAC instance
589	* @param DAC_Channel This parameter can be one of the following values:
590	* @arg @ref LL_DAC_CHANNEL_1
591	* @arg @ref LL_DAC_CHANNEL_2
592	* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
593	*/
594	__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
595	{
596	return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
597	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
598	);
599	}
600
601	/**
602	* @brief Set the conversion trigger source for the selected DAC channel.
603	* @note For conversion trigger source to be effective, DAC trigger
604	* must be enabled using function @ref LL_DAC_EnableTrigger().
605	* @note To set conversion trigger source, DAC channel must be disabled.
606	* Otherwise, the setting is discarded.
607	* @note Availability of parameters of trigger sources from timer
608	* depends on timers availability on the selected device.
609	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
610	* CR TSEL2 LL_DAC_SetTriggerSource
611	* @param DACx DAC instance
612	* @param DAC_Channel This parameter can be one of the following values:
613	* @arg @ref LL_DAC_CHANNEL_1
614	* @arg @ref LL_DAC_CHANNEL_2
615	* @param TriggerSource This parameter can be one of the following values:
616	* @arg @ref LL_DAC_TRIG_SOFTWARE
617	* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
618	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
619	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
620	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
621	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
622	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
623	* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
624	* @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
625	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
626	* @retval None
627	*/
628	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
629	{
630	MODIFY_REG(DACx->CR,
631	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
632	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
633	}
634
635	/**
636	* @brief Get the conversion trigger source for the selected DAC channel.
637	* @note For conversion trigger source to be effective, DAC trigger
638	* must be enabled using function @ref LL_DAC_EnableTrigger().
639	* @note Availability of parameters of trigger sources from timer
640	* depends on timers availability on the selected device.
641	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
642	* CR TSEL2 LL_DAC_GetTriggerSource
643	* @param DACx DAC instance
644	* @param DAC_Channel This parameter can be one of the following values:
645	* @arg @ref LL_DAC_CHANNEL_1
646	* @arg @ref LL_DAC_CHANNEL_2
647	* @retval Returned value can be one of the following values:
648	* @arg @ref LL_DAC_TRIG_SOFTWARE
649	* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
650	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
651	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
652	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
653	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
654	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
655	* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
656	* @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
657	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
658	*/
659	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
660	{
661	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
662	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
663	);
664	}
665
666	/**
667	* @brief Set the waveform automatic generation mode
668	* for the selected DAC channel.
669	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
670	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
671	* @param DACx DAC instance
672	* @param DAC_Channel This parameter can be one of the following values:
673	* @arg @ref LL_DAC_CHANNEL_1
674	* @arg @ref LL_DAC_CHANNEL_2
675	* @param WaveAutoGeneration This parameter can be one of the following values:
676	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
677	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
678	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
679	* @retval None
680	*/
681	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
682	{
683	MODIFY_REG(DACx->CR,
684	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
685	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
686	}
687
688	/**
689	* @brief Get the waveform automatic generation mode
690	* for the selected DAC channel.
691	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
692	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
693	* @param DACx DAC instance
694	* @param DAC_Channel This parameter can be one of the following values:
695	* @arg @ref LL_DAC_CHANNEL_1
696	* @arg @ref LL_DAC_CHANNEL_2
697	* @retval Returned value can be one of the following values:
698	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
699	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
700	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
701	*/
702	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
703	{
704	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
705	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
706	);
707	}
708
709	/**
710	* @brief Set the noise waveform generation for the selected DAC channel:
711	* Noise mode and parameters LFSR (linear feedback shift register).
712	* @note For wave generation to be effective, DAC channel
713	* wave generation mode must be enabled using
714	* function @ref LL_DAC_SetWaveAutoGeneration().
715	* @note This setting can be set when the selected DAC channel is disabled
716	* (otherwise, the setting operation is ignored).
717	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
718	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
719	* @param DACx DAC instance
720	* @param DAC_Channel This parameter can be one of the following values:
721	* @arg @ref LL_DAC_CHANNEL_1
722	* @arg @ref LL_DAC_CHANNEL_2
723	* @param NoiseLFSRMask This parameter can be one of the following values:
724	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
725	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
726	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
727	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
728	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
729	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
730	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
731	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
732	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
733	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
734	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
735	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
736	* @retval None
737	*/
738	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
739	{
740	MODIFY_REG(DACx->CR,
741	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
742	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
743	}
744
745	/**
746	* @brief Get the noise waveform generation for the selected DAC channel:
747	* Noise mode and parameters LFSR (linear feedback shift register).
748	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
749	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
750	* @param DACx DAC instance
751	* @param DAC_Channel This parameter can be one of the following values:
752	* @arg @ref LL_DAC_CHANNEL_1
753	* @arg @ref LL_DAC_CHANNEL_2
754	* @retval Returned value can be one of the following values:
755	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
756	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
757	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
758	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
759	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
760	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
761	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
762	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
763	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
764	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
765	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
766	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
767	*/
768	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
769	{
770	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
771	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
772	);
773	}
774
775	/**
776	* @brief Set the triangle waveform generation for the selected DAC channel:
777	* triangle mode and amplitude.
778	* @note For wave generation to be effective, DAC channel
779	* wave generation mode must be enabled using
780	* function @ref LL_DAC_SetWaveAutoGeneration().
781	* @note This setting can be set when the selected DAC channel is disabled
782	* (otherwise, the setting operation is ignored).
783	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
784	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
785	* @param DACx DAC instance
786	* @param DAC_Channel This parameter can be one of the following values:
787	* @arg @ref LL_DAC_CHANNEL_1
788	* @arg @ref LL_DAC_CHANNEL_2
789	* @param TriangleAmplitude This parameter can be one of the following values:
790	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
791	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
792	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
793	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
794	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
795	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
796	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
797	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
798	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
799	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
800	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
801	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
802	* @retval None
803	*/
804	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
805	uint32_t TriangleAmplitude)
806	{
807	MODIFY_REG(DACx->CR,
808	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
809	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
810	}
811
812	/**
813	* @brief Get the triangle waveform generation for the selected DAC channel:
814	* triangle mode and amplitude.
815	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
816	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
817	* @param DACx DAC instance
818	* @param DAC_Channel This parameter can be one of the following values:
819	* @arg @ref LL_DAC_CHANNEL_1
820	* @arg @ref LL_DAC_CHANNEL_2
821	* @retval Returned value can be one of the following values:
822	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
823	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
824	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
825	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
826	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
827	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
828	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
829	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
830	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
831	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
832	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
833	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
834	*/
835	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
836	{
837	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
838	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
839	);
840	}
841
842	/**
843	* @brief Set the output for the selected DAC channel.
844	* @note This function set several features:
845	* - mode normal or sample-and-hold
846	* - buffer
847	* - connection to GPIO or internal path.
848	* These features can also be set individually using
849	* dedicated functions:
850	* - @ref LL_DAC_SetOutputBuffer()
851	* - @ref LL_DAC_SetOutputMode()
852	* - @ref LL_DAC_SetOutputConnection()
853	* @note On this STM32 serie, output connection depends on output mode
854	* (normal or sample and hold) and output buffer state.
855	* - if output connection is set to internal path and output buffer
856	* is enabled (whatever output mode):
857	* output connection is also connected to GPIO pin
858	* (both connections to GPIO pin and internal path).
859	* - if output connection is set to GPIO pin, output buffer
860	* is disabled, output mode set to sample and hold:
861	* output connection is also connected to internal path
862	* (both connections to GPIO pin and internal path).
863	* @note Mode sample-and-hold requires an external capacitor
864	* to be connected between DAC channel output and ground.
865	* Capacitor value depends on load on DAC channel output and
866	* sample-and-hold timings configured.
867	* As indication, capacitor typical value is 100nF
868	* (refer to device datasheet, parameter "CSH").
869	* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
870	* CR MODE2 LL_DAC_ConfigOutput
871	* @param DACx DAC instance
872	* @param DAC_Channel This parameter can be one of the following values:
873	* @arg @ref LL_DAC_CHANNEL_1
874	* @arg @ref LL_DAC_CHANNEL_2
875	* @param OutputMode This parameter can be one of the following values:
876	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
877	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
878	* @param OutputBuffer This parameter can be one of the following values:
879	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
880	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
881	* @param OutputConnection This parameter can be one of the following values:
882	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
883	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
884	* @retval None
885	*/
886	__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
887	uint32_t OutputBuffer, uint32_t OutputConnection)
888	{
889	MODIFY_REG(DACx->MCR,
890	(DAC_MCR_MODE1_2 \| DAC_MCR_MODE1_1 \| DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
891	(OutputMode \| OutputBuffer \| OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
892	}
893
894	/**
895	* @brief Set the output mode normal or sample-and-hold
896	* for the selected DAC channel.
897	* @note Mode sample-and-hold requires an external capacitor
898	* to be connected between DAC channel output and ground.
899	* Capacitor value depends on load on DAC channel output and
900	* sample-and-hold timings configured.
901	* As indication, capacitor typical value is 100nF
902	* (refer to device datasheet, parameter "CSH").
903	* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
904	* CR MODE2 LL_DAC_SetOutputMode
905	* @param DACx DAC instance
906	* @param DAC_Channel This parameter can be one of the following values:
907	* @arg @ref LL_DAC_CHANNEL_1
908	* @arg @ref LL_DAC_CHANNEL_2
909	* @param OutputMode This parameter can be one of the following values:
910	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
911	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
912	* @retval None
913	*/
914	__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
915	{
916	MODIFY_REG(DACx->MCR,
917	(uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
918	OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
919	}
920
921	/**
922	* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
923	* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
924	* CR MODE2 LL_DAC_GetOutputMode
925	* @param DACx DAC instance
926	* @param DAC_Channel This parameter can be one of the following values:
927	* @arg @ref LL_DAC_CHANNEL_1
928	* @arg @ref LL_DAC_CHANNEL_2
929	* @retval Returned value can be one of the following values:
930	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
931	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
932	*/
933	__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
934	{
935	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
936	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
937	);
938	}
939
940	/**
941	* @brief Set the output buffer for the selected DAC channel.
942	* @note On this STM32 serie, when buffer is enabled, its offset can be
943	* trimmed: factory calibration default values can be
944	* replaced by user trimming values, using function
945	* @ref LL_DAC_SetTrimmingValue().
946	* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
947	* CR MODE2 LL_DAC_SetOutputBuffer
948	* @param DACx DAC instance
949	* @param DAC_Channel This parameter can be one of the following values:
950	* @arg @ref LL_DAC_CHANNEL_1
951	* @arg @ref LL_DAC_CHANNEL_2
952	* @param OutputBuffer This parameter can be one of the following values:
953	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
954	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
955	* @retval None
956	*/
957	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
958	{
959	MODIFY_REG(DACx->MCR,
960	(uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
961	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
962	}
963
964	/**
965	* @brief Get the output buffer state for the selected DAC channel.
966	* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
967	* CR MODE2 LL_DAC_GetOutputBuffer
968	* @param DACx DAC instance
969	* @param DAC_Channel This parameter can be one of the following values:
970	* @arg @ref LL_DAC_CHANNEL_1
971	* @arg @ref LL_DAC_CHANNEL_2
972	* @retval Returned value can be one of the following values:
973	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
974	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
975	*/
976	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
977	{
978	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
979	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
980	);
981	}
982
983	/**
984	* @brief Set the output connection for the selected DAC channel.
985	* @note On this STM32 serie, output connection depends on output mode (normal or
986	* sample and hold) and output buffer state.
987	* - if output connection is set to internal path and output buffer
988	* is enabled (whatever output mode):
989	* output connection is also connected to GPIO pin
990	* (both connections to GPIO pin and internal path).
991	* - if output connection is set to GPIO pin, output buffer
992	* is disabled, output mode set to sample and hold:
993	* output connection is also connected to internal path
994	* (both connections to GPIO pin and internal path).
995	* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
996	* CR MODE2 LL_DAC_SetOutputConnection
997	* @param DACx DAC instance
998	* @param DAC_Channel This parameter can be one of the following values:
999	* @arg @ref LL_DAC_CHANNEL_1
1000	* @arg @ref LL_DAC_CHANNEL_2
1001	* @param OutputConnection This parameter can be one of the following values:
1002	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1003	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1004	* @retval None
1005	*/
1006	__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1007	{
1008	MODIFY_REG(DACx->MCR,
1009	(uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1010	OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1011	}
1012
1013	/**
1014	* @brief Get the output connection for the selected DAC channel.
1015	* @note On this STM32 serie, output connection depends on output mode (normal or
1016	* sample and hold) and output buffer state.
1017	* - if output connection is set to internal path and output buffer
1018	* is enabled (whatever output mode):
1019	* output connection is also connected to GPIO pin
1020	* (both connections to GPIO pin and internal path).
1021	* - if output connection is set to GPIO pin, output buffer
1022	* is disabled, output mode set to sample and hold:
1023	* output connection is also connected to internal path
1024	* (both connections to GPIO pin and internal path).
1025	* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1026	* CR MODE2 LL_DAC_GetOutputConnection
1027	* @param DACx DAC instance
1028	* @param DAC_Channel This parameter can be one of the following values:
1029	* @arg @ref LL_DAC_CHANNEL_1
1030	* @arg @ref LL_DAC_CHANNEL_2
1031	* @retval Returned value can be one of the following values:
1032	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1033	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1034	*/
1035	__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1036	{
1037	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1038	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1039	);
1040	}
1041
1042	/**
1043	* @brief Set the sample-and-hold timing for the selected DAC channel:
1044	* sample time
1045	* @note Sample time must be set when DAC channel is disabled
1046	* or during DAC operation when DAC channel flag BWSTx is reset,
1047	* otherwise the setting is ignored.
1048	* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1049	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1050	* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1051	* @param DACx DAC instance
1052	* @param DAC_Channel This parameter can be one of the following values:
1053	* @arg @ref LL_DAC_CHANNEL_1
1054	* @arg @ref LL_DAC_CHANNEL_2
1055	* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1056	* @retval None
1057	*/
1058	__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1059	{
1060	__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1061
1062	MODIFY_REG(*preg,
1063	DAC_SHSR1_TSAMPLE1,
1064	SampleTime);
1065	}
1066
1067	/**
1068	* @brief Get the sample-and-hold timing for the selected DAC channel:
1069	* sample time
1070	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1071	* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1072	* @param DACx DAC instance
1073	* @param DAC_Channel This parameter can be one of the following values:
1074	* @arg @ref LL_DAC_CHANNEL_1
1075	* @arg @ref LL_DAC_CHANNEL_2
1076	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1077	*/
1078	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1079	{
1080	__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1081
1082	return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1083	}
1084
1085	/**
1086	* @brief Set the sample-and-hold timing for the selected DAC channel:
1087	* hold time
1088	* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1089	* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1090	* @param DACx DAC instance
1091	* @param DAC_Channel This parameter can be one of the following values:
1092	* @arg @ref LL_DAC_CHANNEL_1
1093	* @arg @ref LL_DAC_CHANNEL_2
1094	* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1095	* @retval None
1096	*/
1097	__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1098	{
1099	MODIFY_REG(DACx->SHHR,
1100	DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1101	HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1102	}
1103
1104	/**
1105	* @brief Get the sample-and-hold timing for the selected DAC channel:
1106	* hold time
1107	* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1108	* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1109	* @param DACx DAC instance
1110	* @param DAC_Channel This parameter can be one of the following values:
1111	* @arg @ref LL_DAC_CHANNEL_1
1112	* @arg @ref LL_DAC_CHANNEL_2
1113	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1114	*/
1115	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1116	{
1117	return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1118	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1119	);
1120	}
1121
1122	/**
1123	* @brief Set the sample-and-hold timing for the selected DAC channel:
1124	* refresh time
1125	* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1126	* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1127	* @param DACx DAC instance
1128	* @param DAC_Channel This parameter can be one of the following values:
1129	* @arg @ref LL_DAC_CHANNEL_1
1130	* @arg @ref LL_DAC_CHANNEL_2
1131	* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1132	* @retval None
1133	*/
1134	__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1135	{
1136	MODIFY_REG(DACx->SHRR,
1137	DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1138	RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1139	}
1140
1141	/**
1142	* @brief Get the sample-and-hold timing for the selected DAC channel:
1143	* refresh time
1144	* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1145	* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1146	* @param DACx DAC instance
1147	* @param DAC_Channel This parameter can be one of the following values:
1148	* @arg @ref LL_DAC_CHANNEL_1
1149	* @arg @ref LL_DAC_CHANNEL_2
1150	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
1151	*/
1152	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1153	{
1154	return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1155	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1156	);
1157	}
1158
1159	/**
1160	* @}
1161	*/
1162
1163	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
1164	* @{
1165	*/
1166
1167	/**
1168	* @brief Enable DAC DMA transfer request of the selected channel.
1169	* @note To configure DMA source address (peripheral address),
1170	* use function @ref LL_DAC_DMA_GetRegAddr().
1171	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1172	* CR DMAEN2 LL_DAC_EnableDMAReq
1173	* @param DACx DAC instance
1174	* @param DAC_Channel This parameter can be one of the following values:
1175	* @arg @ref LL_DAC_CHANNEL_1
1176	* @arg @ref LL_DAC_CHANNEL_2
1177	* @retval None
1178	*/
1179	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1180	{
1181	SET_BIT(DACx->CR,
1182	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1183	}
1184
1185	/**
1186	* @brief Disable DAC DMA transfer request of the selected channel.
1187	* @note To configure DMA source address (peripheral address),
1188	* use function @ref LL_DAC_DMA_GetRegAddr().
1189	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1190	* CR DMAEN2 LL_DAC_DisableDMAReq
1191	* @param DACx DAC instance
1192	* @param DAC_Channel This parameter can be one of the following values:
1193	* @arg @ref LL_DAC_CHANNEL_1
1194	* @arg @ref LL_DAC_CHANNEL_2
1195	* @retval None
1196	*/
1197	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1198	{
1199	CLEAR_BIT(DACx->CR,
1200	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1201	}
1202
1203	/**
1204	* @brief Get DAC DMA transfer request state of the selected channel.
1205	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1206	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1207	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
1208	* @param DACx DAC instance
1209	* @param DAC_Channel This parameter can be one of the following values:
1210	* @arg @ref LL_DAC_CHANNEL_1
1211	* @arg @ref LL_DAC_CHANNEL_2
1212	* @retval State of bit (1 or 0).
1213	*/
1214	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1215	{
1216	return ((READ_BIT(DACx->CR,
1217	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1218	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1219	}
1220
1221	/**
1222	* @brief Function to help to configure DMA transfer to DAC: retrieve the
1223	* DAC register address from DAC instance and a list of DAC registers
1224	* intended to be used (most commonly) with DMA transfer.
1225	* @note These DAC registers are data holding registers:
1226	* when DAC conversion is requested, DAC generates a DMA transfer
1227	* request to have data available in DAC data holding registers.
1228	* @note This macro is intended to be used with LL DMA driver, refer to
1229	* function "LL_DMA_ConfigAddresses()".
1230	* Example:
1231	* LL_DMA_ConfigAddresses(DMA1,
1232	* LL_DMA_CHANNEL_1,
1233	* (uint32_t)&< array or variable >,
1234	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1235	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1236	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1237	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1238	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1239	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1240	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1241	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1242	* @param DACx DAC instance
1243	* @param DAC_Channel This parameter can be one of the following values:
1244	* @arg @ref LL_DAC_CHANNEL_1
1245	* @arg @ref LL_DAC_CHANNEL_2
1246	* @param Register This parameter can be one of the following values:
1247	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1248	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1249	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1250	* @retval DAC register address
1251	*/
1252	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1253	{
1254	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1255	/* DAC channel selected. */
1256	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
1257	((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1258	}
1259	/**
1260	* @}
1261	*/
1262
1263	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1264	* @{
1265	*/
1266
1267	/**
1268	* @brief Enable DAC selected channel.
1269	* @rmtoll CR EN1 LL_DAC_Enable\n
1270	* CR EN2 LL_DAC_Enable
1271	* @note After enable from off state, DAC channel requires a delay
1272	* for output voltage to reach accuracy +/- 1 LSB.
1273	* Refer to device datasheet, parameter "tWAKEUP".
1274	* @param DACx DAC instance
1275	* @param DAC_Channel This parameter can be one of the following values:
1276	* @arg @ref LL_DAC_CHANNEL_1
1277	* @arg @ref LL_DAC_CHANNEL_2
1278	* @retval None
1279	*/
1280	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1281	{
1282	SET_BIT(DACx->CR,
1283	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1284	}
1285
1286	/**
1287	* @brief Disable DAC selected channel.
1288	* @rmtoll CR EN1 LL_DAC_Disable\n
1289	* CR EN2 LL_DAC_Disable
1290	* @param DACx DAC instance
1291	* @param DAC_Channel This parameter can be one of the following values:
1292	* @arg @ref LL_DAC_CHANNEL_1
1293	* @arg @ref LL_DAC_CHANNEL_2
1294	* @retval None
1295	*/
1296	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1297	{
1298	CLEAR_BIT(DACx->CR,
1299	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1300	}
1301
1302	/**
1303	* @brief Get DAC enable state of the selected channel.
1304	* (0: DAC channel is disabled, 1: DAC channel is enabled)
1305	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
1306	* CR EN2 LL_DAC_IsEnabled
1307	* @param DACx DAC instance
1308	* @param DAC_Channel This parameter can be one of the following values:
1309	* @arg @ref LL_DAC_CHANNEL_1
1310	* @arg @ref LL_DAC_CHANNEL_2
1311	* @retval State of bit (1 or 0).
1312	*/
1313	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1314	{
1315	return ((READ_BIT(DACx->CR,
1316	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1317	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1318	}
1319
1320	/**
1321	* @brief Enable DAC trigger of the selected channel.
1322	* @note - If DAC trigger is disabled, DAC conversion is performed
1323	* automatically once the data holding register is updated,
1324	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1325	* @ref LL_DAC_ConvertData12RightAligned(), ...
1326	* - If DAC trigger is enabled, DAC conversion is performed
1327	* only when a hardware of software trigger event is occurring.
1328	* Select trigger source using
1329	* function @ref LL_DAC_SetTriggerSource().
1330	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1331	* CR TEN2 LL_DAC_EnableTrigger
1332	* @param DACx DAC instance
1333	* @param DAC_Channel This parameter can be one of the following values:
1334	* @arg @ref LL_DAC_CHANNEL_1
1335	* @arg @ref LL_DAC_CHANNEL_2
1336	* @retval None
1337	*/
1338	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1339	{
1340	SET_BIT(DACx->CR,
1341	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1342	}
1343
1344	/**
1345	* @brief Disable DAC trigger of the selected channel.
1346	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1347	* CR TEN2 LL_DAC_DisableTrigger
1348	* @param DACx DAC instance
1349	* @param DAC_Channel This parameter can be one of the following values:
1350	* @arg @ref LL_DAC_CHANNEL_1
1351	* @arg @ref LL_DAC_CHANNEL_2
1352	* @retval None
1353	*/
1354	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1355	{
1356	CLEAR_BIT(DACx->CR,
1357	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1358	}
1359
1360	/**
1361	* @brief Get DAC trigger state of the selected channel.
1362	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1363	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1364	* CR TEN2 LL_DAC_IsTriggerEnabled
1365	* @param DACx DAC instance
1366	* @param DAC_Channel This parameter can be one of the following values:
1367	* @arg @ref LL_DAC_CHANNEL_1
1368	* @arg @ref LL_DAC_CHANNEL_2
1369	* @retval State of bit (1 or 0).
1370	*/
1371	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1372	{
1373	return ((READ_BIT(DACx->CR,
1374	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1375	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1376	}
1377
1378	/**
1379	* @brief Trig DAC conversion by software for the selected DAC channel.
1380	* @note Preliminarily, DAC trigger must be set to software trigger
1381	* using function
1382	* @ref LL_DAC_Init()
1383	* @ref LL_DAC_SetTriggerSource()
1384	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
1385	* and DAC trigger must be enabled using
1386	* function @ref LL_DAC_EnableTrigger().
1387	* @note For devices featuring DAC with 2 channels: this function
1388	* can perform a SW start of both DAC channels simultaneously.
1389	* Two channels can be selected as parameter.
1390	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
1391	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1392	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1393	* @param DACx DAC instance
1394	* @param DAC_Channel This parameter can a combination of the following values:
1395	* @arg @ref LL_DAC_CHANNEL_1
1396	* @arg @ref LL_DAC_CHANNEL_2
1397	* @retval None
1398	*/
1399	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1400	{
1401	SET_BIT(DACx->SWTRIGR,
1402	(DAC_Channel & DAC_SWTR_CHX_MASK));
1403	}
1404
1405	/**
1406	* @brief Set the data to be loaded in the data holding register
1407	* in format 12 bits left alignment (LSB aligned on bit 0),
1408	* for the selected DAC channel.
1409	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1410	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1411	* @param DACx DAC instance
1412	* @param DAC_Channel This parameter can be one of the following values:
1413	* @arg @ref LL_DAC_CHANNEL_1
1414	* @arg @ref LL_DAC_CHANNEL_2
1415	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1416	* @retval None
1417	*/
1418	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1419	{
1420	__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1421
1422	MODIFY_REG(*preg,
1423	DAC_DHR12R1_DACC1DHR,
1424	Data);
1425	}
1426
1427	/**
1428	* @brief Set the data to be loaded in the data holding register
1429	* in format 12 bits left alignment (MSB aligned on bit 15),
1430	* for the selected DAC channel.
1431	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1432	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1433	* @param DACx DAC instance
1434	* @param DAC_Channel This parameter can be one of the following values:
1435	* @arg @ref LL_DAC_CHANNEL_1
1436	* @arg @ref LL_DAC_CHANNEL_2
1437	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1438	* @retval None
1439	*/
1440	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1441	{
1442	__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1443
1444	MODIFY_REG(*preg,
1445	DAC_DHR12L1_DACC1DHR,
1446	Data);
1447	}
1448
1449	/**
1450	* @brief Set the data to be loaded in the data holding register
1451	* in format 8 bits left alignment (LSB aligned on bit 0),
1452	* for the selected DAC channel.
1453	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1454	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1455	* @param DACx DAC instance
1456	* @param DAC_Channel This parameter can be one of the following values:
1457	* @arg @ref LL_DAC_CHANNEL_1
1458	* @arg @ref LL_DAC_CHANNEL_2
1459	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1460	* @retval None
1461	*/
1462	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1463	{
1464	__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1465
1466	MODIFY_REG(*preg,
1467	DAC_DHR8R1_DACC1DHR,
1468	Data);
1469	}
1470
1471
1472	/**
1473	* @brief Set the data to be loaded in the data holding register
1474	* in format 12 bits left alignment (LSB aligned on bit 0),
1475	* for both DAC channels.
1476	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1477	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1478	* @param DACx DAC instance
1479	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1480	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1481	* @retval None
1482	*/
1483	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1484	uint32_t DataChannel2)
1485	{
1486	MODIFY_REG(DACx->DHR12RD,
1487	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
1488	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
1489	}
1490
1491	/**
1492	* @brief Set the data to be loaded in the data holding register
1493	* in format 12 bits left alignment (MSB aligned on bit 15),
1494	* for both DAC channels.
1495	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1496	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1497	* @param DACx DAC instance
1498	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1499	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1500	* @retval None
1501	*/
1502	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1503	uint32_t DataChannel2)
1504	{
1505	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1506	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1507	/* the 4 LSB must be taken into account for the shift value. */
1508	MODIFY_REG(DACx->DHR12LD,
1509	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
1510	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
1511	}
1512
1513	/**
1514	* @brief Set the data to be loaded in the data holding register
1515	* in format 8 bits left alignment (LSB aligned on bit 0),
1516	* for both DAC channels.
1517	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1518	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1519	* @param DACx DAC instance
1520	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1521	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1522	* @retval None
1523	*/
1524	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1525	uint32_t DataChannel2)
1526	{
1527	MODIFY_REG(DACx->DHR8RD,
1528	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
1529	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
1530	}
1531
1532
1533	/**
1534	* @brief Retrieve output data currently generated for the selected DAC channel.
1535	* @note Whatever alignment and resolution settings
1536	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1537	* @ref LL_DAC_ConvertData12RightAligned(), ...),
1538	* output data format is 12 bits right aligned (LSB aligned on bit 0).
1539	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1540	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1541	* @param DACx DAC instance
1542	* @param DAC_Channel This parameter can be one of the following values:
1543	* @arg @ref LL_DAC_CHANNEL_1
1544	* @arg @ref LL_DAC_CHANNEL_2
1545	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1546	*/
1547	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1548	{
1549	__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1550
1551	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1552	}
1553
1554	/**
1555	* @}
1556	*/
1557
1558	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1559	* @{
1560	*/
1561	/**
1562	* @brief Get DAC calibration offset flag for DAC channel 1
1563	* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1564	* @param DACx DAC instance
1565	* @retval State of bit (1 or 0).
1566	*/
1567	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1568	{
1569	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1570	}
1571
1572
1573	/**
1574	* @brief Get DAC calibration offset flag for DAC channel 2
1575	* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1576	* @param DACx DAC instance
1577	* @retval State of bit (1 or 0).
1578	*/
1579	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1580	{
1581	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1582	}
1583
1584
1585	/**
1586	* @brief Get DAC busy writing sample time flag for DAC channel 1
1587	* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1588	* @param DACx DAC instance
1589	* @retval State of bit (1 or 0).
1590	*/
1591	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1592	{
1593	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1594	}
1595
1596
1597	/**
1598	* @brief Get DAC busy writing sample time flag for DAC channel 2
1599	* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1600	* @param DACx DAC instance
1601	* @retval State of bit (1 or 0).
1602	*/
1603	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1604	{
1605	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1606	}
1607
1608
1609	/**
1610	* @brief Get DAC underrun flag for DAC channel 1
1611	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1612	* @param DACx DAC instance
1613	* @retval State of bit (1 or 0).
1614	*/
1615	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1616	{
1617	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1618	}
1619
1620
1621	/**
1622	* @brief Get DAC underrun flag for DAC channel 2
1623	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1624	* @param DACx DAC instance
1625	* @retval State of bit (1 or 0).
1626	*/
1627	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1628	{
1629	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1630	}
1631
1632
1633	/**
1634	* @brief Clear DAC underrun flag for DAC channel 1
1635	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1636	* @param DACx DAC instance
1637	* @retval None
1638	*/
1639	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1640	{
1641	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1642	}
1643
1644
1645	/**
1646	* @brief Clear DAC underrun flag for DAC channel 2
1647	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1648	* @param DACx DAC instance
1649	* @retval None
1650	*/
1651	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1652	{
1653	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1654	}
1655
1656
1657	/**
1658	* @}
1659	*/
1660
1661	/** @defgroup DAC_LL_EF_IT_Management IT management
1662	* @{
1663	*/
1664
1665	/**
1666	* @brief Enable DMA underrun interrupt for DAC channel 1
1667	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1668	* @param DACx DAC instance
1669	* @retval None
1670	*/
1671	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1672	{
1673	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1674	}
1675
1676
1677	/**
1678	* @brief Enable DMA underrun interrupt for DAC channel 2
1679	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1680	* @param DACx DAC instance
1681	* @retval None
1682	*/
1683	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1684	{
1685	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1686	}
1687
1688
1689	/**
1690	* @brief Disable DMA underrun interrupt for DAC channel 1
1691	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1692	* @param DACx DAC instance
1693	* @retval None
1694	*/
1695	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1696	{
1697	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1698	}
1699
1700
1701	/**
1702	* @brief Disable DMA underrun interrupt for DAC channel 2
1703	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1704	* @param DACx DAC instance
1705	* @retval None
1706	*/
1707	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1708	{
1709	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1710	}
1711
1712
1713	/**
1714	* @brief Get DMA underrun interrupt for DAC channel 1
1715	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1716	* @param DACx DAC instance
1717	* @retval State of bit (1 or 0).
1718	*/
1719	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1720	{
1721	return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1722	}
1723
1724
1725	/**
1726	* @brief Get DMA underrun interrupt for DAC channel 2
1727	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1728	* @param DACx DAC instance
1729	* @retval State of bit (1 or 0).
1730	*/
1731	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1732	{
1733	return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1734	}
1735
1736
1737	/**
1738	* @}
1739	*/
1740
1741	#if defined(USE_FULL_LL_DRIVER)
1742	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1743	* @{
1744	*/
1745
1746	ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1747	ErrorStatus LL_DAC_Init(DAC_TypeDef DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef DAC_InitStruct);
1748	void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1749
1750	/**
1751	* @}
1752	*/
1753	#endif /* USE_FULL_LL_DRIVER */
1754
1755	/**
1756	* @}
1757	*/
1758
1759	/**
1760	* @}
1761	*/
1762
1763	#endif /* DAC1 */
1764
1765	/**
1766	* @}
1767	*/
1768
1769	#ifdef __cplusplus
1770	}
1771	#endif
1772
1773	#endif /* STM32G0xx_LL_DAC_H */
1774
1775	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dac.h

Download in other formats: