source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h

Last change on this file was 6, checked in by f.jahn, 3 months ago
File size: 50.2 KB
Line 
1/**
2  ******************************************************************************
3  * @file    stm32g0xx_ll_pwr.h
4  * @author  MCD Application Team
5  * @brief   Header file of PWR LL module.
6  ******************************************************************************
7  * @attention
8  *
9  * Copyright (c) 2018 STMicroelectronics.
10  * All rights reserved.
11  *
12  * This software is licensed under terms that can be found in the LICENSE file
13  * in the root directory of this software component.
14  * If no LICENSE file comes with this software, it is provided AS-IS.
15  *
16  ******************************************************************************
17  */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32G0xx_LL_PWR_H
21#define STM32G0xx_LL_PWR_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32g0xx.h"
29
30/** @addtogroup STM32G0xx_LL_Driver
31  * @{
32  */
33
34#if defined(PWR)
35
36/** @defgroup PWR_LL PWR
37  * @{
38  */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
44
45/* Private macros ------------------------------------------------------------*/
46
47/* Exported types ------------------------------------------------------------*/
48/* Exported constants --------------------------------------------------------*/
49/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
50  * @{
51  */
52
53/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
54  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
55  * @{
56  */
57#define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
58#define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
59#define LL_PWR_SCR_CWUF6                   PWR_SCR_CWUF6
60#define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
61#define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
62#if defined(PWR_CR3_EWUP3)
63#define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
64#endif /* PWR_CR3_EWUP3 */
65#define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
66#define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
67/**
68  * @}
69  */
70
71/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
72  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
73  * @{
74  */
75#define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
76#define LL_PWR_SR1_SBF                     PWR_SR1_SBF
77#define LL_PWR_SR1_WUF6                    PWR_SR1_WUF6
78#define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
79#define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
80#if defined(PWR_CR3_EWUP3)
81#define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
82#endif /* PWR_CR3_EWUP3 */
83#define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
84#define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
85#if defined(PWR_SR2_PVDO)
86#define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
87#endif /* PWR_SR2_PVDO */
88#define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
89#define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
90#define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
91/**
92  * @}
93  */
94
95/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
96  * @{
97  */
98#define LL_PWR_REGU_VOLTAGE_SCALE1         PWR_CR1_VOS_0
99#define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
100/**
101  * @}
102  */
103
104/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
105  * @{
106  */
107#define LL_PWR_MODE_STOP0                  (0x00000000UL)
108#define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_0)
109#define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
110#if defined (PWR_CR1_LPMS_2)
111#define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_2)
112#endif /* PWR_CR1_LPMS_2 */
113/**
114  * @}
115  */
116
117#if defined(PWR_CR2_PVDE)
118/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
119  * @{
120  */
121#define LL_PWR_PVDLLEVEL_0                  0x000000000u                                /* VPVD0 > 2.05 V */
122#define LL_PWR_PVDLLEVEL_1                  (PWR_CR2_PVDFT_0)                           /* VPVD0 > 2.2 V */
123#define LL_PWR_PVDLLEVEL_2                  (PWR_CR2_PVDFT_1)                           /* VPVD1 > 2.36 V */
124#define LL_PWR_PVDLLEVEL_3                  (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0)         /* VPVD2 > 2.52 V */
125#define LL_PWR_PVDLLEVEL_4                  (PWR_CR2_PVDFT_2)                           /* VPVD3 > 2.64 V */
126#define LL_PWR_PVDLLEVEL_5                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)         /* VPVD4 > 2.81 V */
127#define LL_PWR_PVDLLEVEL_6                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)         /* VPVD5 > 2.91 V */
128
129#define LL_PWR_PVDHLEVEL_0                  0x00000000u                                 /* VPDD0 > 2.15 V */
130#define LL_PWR_PVDHLEVEL_1                  (PWR_CR2_PVDRT_0)                           /* VPVD1 > 2.3 V */
131#define LL_PWR_PVDHLEVEL_2                  (PWR_CR2_PVDRT_1)                           /* VPVD1 > 2.46 V */
132#define LL_PWR_PVDHLEVEL_3                  (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)         /* VPVD2 > 2.62 V */
133#define LL_PWR_PVDHLEVEL_4                  (PWR_CR2_PVDRT_2)                           /* VPVD3 > 2.74 V */
134#define LL_PWR_PVDHLEVEL_5                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)         /* VPVD4 > 2.91 V */
135#define LL_PWR_PVDHLEVEL_6                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)         /* VPVD5 > 3.01 V */
136#define LL_PWR_PVDHLEVEL_7                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)  /* External input analog voltage   (Compare internally to VREFINT) */
137/**
138  * @}
139  */
140#endif /* PWR_CR2_PVDE */
141
142#if defined(PWR_PVM_SUPPORT)
143/** @defgroup PWR_LL_EC_PVM_IP PVM_IP
144  * @{
145  */
146#define LL_PWR_PVM_USB                  PWR_CR2_PVMEN_USB                           /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
147/**
148  * @}
149  */
150#endif /* PWR_PVM_SUPPORT */
151
152/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
153  * @{
154  */
155#define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
156#define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
157#if defined(PWR_CR3_EWUP3)
158#define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
159#endif /* PWR_CR3_EWUP3 */
160#define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
161#if defined(PWR_CR3_EWUP5)
162#define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
163#endif /* PWR_CR3_EWUP5 */
164#define LL_PWR_WAKEUP_PIN6                 (PWR_CR3_EWUP6)
165/**
166  * @}
167  */
168
169/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
170  * @{
171  */
172#define LL_PWR_BATTCHARG_RESISTOR_5K       0x000000000u
173#define LL_PWR_BATTCHARG_RESISTOR_1_5K     (PWR_CR4_VBRS)
174/**
175  * @}
176  */
177
178/** @defgroup PWR_LL_EC_GPIO GPIO
179  * @{
180  */
181#define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
182#define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
183#define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
184#define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
185#if defined(GPIOE)
186#define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
187#endif /* GPIOE */
188#define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
189/**
190  * @}
191  */
192
193/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
194  * @{
195  */
196#define LL_PWR_GPIO_BIT_0                  0x00000001u
197#define LL_PWR_GPIO_BIT_1                  0x00000002u
198#define LL_PWR_GPIO_BIT_2                  0x00000004u
199#define LL_PWR_GPIO_BIT_3                  0x00000008u
200#define LL_PWR_GPIO_BIT_4                  0x00000010u
201#define LL_PWR_GPIO_BIT_5                  0x00000020u
202#define LL_PWR_GPIO_BIT_6                  0x00000040u
203#define LL_PWR_GPIO_BIT_7                  0x00000080u
204#define LL_PWR_GPIO_BIT_8                  0x00000100u
205#define LL_PWR_GPIO_BIT_9                  0x00000200u
206#define LL_PWR_GPIO_BIT_10                 0x00000400u
207#define LL_PWR_GPIO_BIT_11                 0x00000800u
208#define LL_PWR_GPIO_BIT_12                 0x00001000u
209#define LL_PWR_GPIO_BIT_13                 0x00002000u
210#define LL_PWR_GPIO_BIT_14                 0x00004000u
211#define LL_PWR_GPIO_BIT_15                 0x00008000u
212/**
213  * @}
214  */
215
216/**
217  * @}
218  */
219
220/* Exported macro ------------------------------------------------------------*/
221/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
222  * @{
223  */
224
225/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
226  * @{
227  */
228
229/**
230  * @brief  Write a value in PWR register
231  * @param  __REG__ Register to be written
232  * @param  __VALUE__ Value to be written in the register
233  * @retval None
234  */
235#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
236
237/**
238  * @brief  Read a value in PWR register
239  * @param  __REG__ Register to be read
240  * @retval Register value
241  */
242#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
243/**
244  * @}
245  */
246
247/**
248  * @}
249  */
250
251
252/* Exported functions --------------------------------------------------------*/
253/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
254  * @{
255  */
256
257/** @defgroup PWR_LL_EF_Configuration Configuration
258  * @{
259  */
260/**
261  * @brief  Set the main internal regulator output voltage
262  * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
263  * @param  VoltageScaling This parameter can be one of the following values:
264  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
265  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
266  * @retval None
267  */
268__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
269{
270  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
271}
272
273/**
274  * @brief  Get the main internal regulator output voltage
275  * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
276  * @retval Returned value can be one of the following values:
277  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
278  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
279  */
280__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
281{
282  return (READ_BIT(PWR->CR1, PWR_CR1_VOS));
283}
284
285/**
286  * @brief  Switch the regulator from main mode to low-power mode
287  * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
288  * @retval None
289  */
290__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
291{
292  SET_BIT(PWR->CR1, PWR_CR1_LPR);
293}
294
295/**
296  * @brief  Switch the regulator from low-power mode to main mode
297  * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
298  * @retval None
299  */
300__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
301{
302  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
303}
304
305/**
306  * @brief  Check if the regulator is in low-power mode
307  * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
308  * @retval State of bit (1 or 0).
309  */
310__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
311{
312  return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
313}
314
315/**
316  * @brief  Switch from run main mode to run low-power mode.
317  * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
318  * @retval None
319  */
320__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
321{
322  LL_PWR_EnableLowPowerRunMode();
323}
324
325/**
326  * @brief  Switch from run main mode to low-power mode.
327  * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
328  * @retval None
329  */
330__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
331{
332  LL_PWR_DisableLowPowerRunMode();
333}
334
335/**
336  * @brief  Enable access to the backup domain
337  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
338  * @retval None
339  */
340__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
341{
342  SET_BIT(PWR->CR1, PWR_CR1_DBP);
343}
344
345/**
346  * @brief  Disable access to the backup domain
347  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
348  * @retval None
349  */
350__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
351{
352  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
353}
354
355/**
356  * @brief  Check if the backup domain is enabled
357  * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
358  * @retval State of bit (1 or 0).
359  */
360__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
361{
362  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
363}
364
365/**
366  * @brief  Enable Flash Power-down mode during low power sleep mode
367  * @rmtoll CR1          CFIPD_SLP     LL_PWR_EnableFlashPowerDownInLPSleep
368  * @retval None
369  */
370__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPSleep(void)
371{
372  SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
373}
374
375/**
376  * @brief  Disable Flash Power-down mode during Low power sleep mode
377  * @rmtoll CR1          CFIPD_SLP     LL_PWR_DisableFlashPowerDownInLPSleep
378  * @retval None
379  */
380__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPSleep(void)
381{
382  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
383}
384
385/**
386  * @brief  Check if flash power-down mode during low power sleep mode domain is enabled
387  * @rmtoll CR1          CFIPD_SLP     LL_PWR_IsEnableFlashPowerDownInLPSleep
388  * @retval State of bit (1 or 0).
389  */
390__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPSleep(void)
391{
392  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL);
393}
394
395/**
396  * @brief  Enable Flash Power-down mode during low power run mode
397  * @rmtoll CR1          CFIPD_RUN     LL_PWR_EnableFlashPowerDownInLPRun
398  * @retval None
399  */
400__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPRun(void)
401{
402  SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
403}
404
405/**
406  * @brief  Disable Flash Power-down mode during Low power run mode
407  * @rmtoll CR1          CFIPD_RUN     LL_PWR_DisableFlashPowerDownInLPRun
408  * @retval None
409  */
410__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPRun(void)
411{
412  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
413}
414
415/**
416  * @brief  Check if flash power-down mode during low power run mode domain is enabled
417  * @rmtoll CR1          CFIPD_RUN     LL_PWR_IsEnableFlashPowerDownInLPRun
418  * @retval State of bit (1 or 0).
419  */
420__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPRun(void)
421{
422  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL);
423}
424
425/**
426  * @brief  Enable Flash Power-down mode during stop mode
427  * @rmtoll CR1          CFIPD_STOP    LL_PWR_EnableFlashPowerDownInStop
428  * @retval None
429  */
430__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
431{
432  SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
433}
434
435/**
436  * @brief  Disable Flash Power-down mode during stop mode
437  * @rmtoll CR1          CFIPD_STOP    LL_PWR_DisableFlashPowerDownInStop
438  * @retval None
439  */
440__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
441{
442  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
443}
444
445/**
446  * @brief  Check if flash power-down mode during stop mode domain is enabled
447  * @rmtoll CR1          CFIPD_STOP    LL_PWR_IsEnableFlashPowerDownInStop
448  * @retval State of bit (1 or 0).
449  */
450__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
451{
452  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
453}
454
455#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
456/**
457  * @brief  Enable VDDIO2 supply
458  * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
459  * @retval None
460  */
461__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
462{
463  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
464}
465
466/**
467  * @brief  Disable VDDIO2 supply
468  * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
469  * @retval None
470  */
471__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
472{
473  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
474}
475
476/**
477  * @brief  Check if VDDIO2 supply is enabled
478  * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
479  * @retval State of bit (1 or 0).
480  */
481__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
482{
483  return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
484}
485#endif /* STM32G0C1xx || STM32G0B1xx */
486
487#if defined(PWR_CR2_USV)
488/**
489  * @brief  Enable VDDUSB supply
490  * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
491  * @retval None
492  */
493__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
494{
495  SET_BIT(PWR->CR2, PWR_CR2_USV);
496}
497
498/**
499  * @brief  Disable VDDUSB supply
500  * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
501  * @retval None
502  */
503__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
504{
505  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
506}
507
508/**
509  * @brief  Check if VDDUSB supply is enabled
510  * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
511  * @retval State of bit (1 or 0).
512  */
513__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
514{
515  return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
516}
517#endif /* PWR_CR2_USV */
518
519#if defined (PWR_PVM_SUPPORT)
520/**
521  * @brief  Enable the Power Voltage Monitoring on a peripheral
522  * @rmtoll CR2          PVMUSB         LL_PWR_EnablePVM
523  * @param  PeriphVoltage This parameter can be one of the following values:
524  *         @arg @ref LL_PWR_PVM_USB (*)
525  *
526  *         (*) value not defined in all devices
527  * @retval None
528  */
529__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
530{
531  SET_BIT(PWR->CR2, PeriphVoltage);
532}
533
534/**
535  * @brief  Disable the Power Voltage Monitoring on a peripheral
536  * @rmtoll CR2          PVMUSB         LL_PWR_DisablePVM
537  * @param  PeriphVoltage This parameter can be one of the following values:
538  *         @arg @ref LL_PWR_PVM_USB (*)
539  *
540  *         (*) value not defined in all devices
541  * @retval None
542  */
543__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
544{
545  CLEAR_BIT(PWR->CR2, PeriphVoltage);
546}
547
548/**
549  * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
550  * @rmtoll CR2          PVMUSB         LL_PWR_IsEnabledPVM
551  * @param  PeriphVoltage This parameter can be one of the following values:
552  *         @arg @ref LL_PWR_PVM_USB (*)
553  *
554  *         (*) value not defined in all devices
555  * @retval State of bit (1 or 0).
556  */
557__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
558{
559  return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
560}
561#endif /* PWR_PVM_SUPPORT */
562
563/**
564  * @brief  Set Low-Power mode
565  * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
566  * @param  LowPowerMode This parameter can be one of the following values:
567  *         @arg @ref LL_PWR_MODE_STOP0
568  *         @arg @ref LL_PWR_MODE_STOP1
569  *         @arg @ref LL_PWR_MODE_STANDBY
570  *         @arg @ref LL_PWR_MODE_SHUTDOWN
571  * @retval None
572  */
573__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
574{
575  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
576}
577
578/**
579  * @brief  Get Low-Power mode
580  * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
581  * @retval Returned value can be one of the following values:
582  *         @arg @ref LL_PWR_MODE_STOP0
583  *         @arg @ref LL_PWR_MODE_STOP1
584  *         @arg @ref LL_PWR_MODE_STANDBY
585  *         @arg @ref LL_PWR_MODE_SHUTDOWN
586  */
587__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
588{
589  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
590}
591
592#if defined (PWR_CR2_PVDE)
593/**
594  * @brief  Configure the high voltage threshold detected by the Power Voltage Detector
595  * @rmtoll CR2          PLS           LL_PWR_SetPVDHighLevel
596  * @param  PVDHighLevel This parameter can be one of the following values:
597  *         @arg @ref LL_PWR_PVDHLEVEL_0
598  *         @arg @ref LL_PWR_PVDHLEVEL_1
599  *         @arg @ref LL_PWR_PVDHLEVEL_2
600  *         @arg @ref LL_PWR_PVDHLEVEL_3
601  *         @arg @ref LL_PWR_PVDHLEVEL_4
602  *         @arg @ref LL_PWR_PVDHLEVEL_5
603  *         @arg @ref LL_PWR_PVDHLEVEL_6
604  *         @arg @ref LL_PWR_PVDHLEVEL_7
605  * @retval None
606  */
607__STATIC_INLINE void LL_PWR_SetPVDHighLevel(uint32_t PVDHighLevel)
608{
609  MODIFY_REG(PWR->CR2, PWR_CR2_PVDRT, PVDHighLevel);
610}
611
612/**
613  * @brief  Get the voltage threshold detection
614  * @rmtoll CR2          PLS           LL_PWR_GetPVDHighLevel
615  * @retval Returned value can be one of the following values:
616  *         @arg @ref LL_PWR_PVDHLEVEL_0
617  *         @arg @ref LL_PWR_PVDHLEVEL_1
618  *         @arg @ref LL_PWR_PVDHLEVEL_2
619  *         @arg @ref LL_PWR_PVDHLEVEL_3
620  *         @arg @ref LL_PWR_PVDHLEVEL_4
621  *         @arg @ref LL_PWR_PVDHLEVEL_5
622  *         @arg @ref LL_PWR_PVDHLEVEL_6
623  *         @arg @ref LL_PWR_PVDHLEVEL_7
624  */
625__STATIC_INLINE uint32_t LL_PWR_GetPVDHighLevel(void)
626{
627  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDRT));
628}
629/**
630  * @brief  Configure the low voltage threshold detected by the Power Voltage Detector
631  * @rmtoll CR2          PLS           LL_PWR_SetPVDLowLevel
632  * @param  PVDLowLevel This parameter can be one of the following values:
633  *         @arg @ref LL_PWR_PVDLLEVEL_0
634  *         @arg @ref LL_PWR_PVDLLEVEL_1
635  *         @arg @ref LL_PWR_PVDLLEVEL_2
636  *         @arg @ref LL_PWR_PVDLLEVEL_3
637  *         @arg @ref LL_PWR_PVDLLEVEL_4
638  *         @arg @ref LL_PWR_PVDLLEVEL_5
639  *         @arg @ref LL_PWR_PVDLLEVEL_6
640  * @retval None
641  */
642__STATIC_INLINE void LL_PWR_SetPVDLowLevel(uint32_t PVDLowLevel)
643{
644  MODIFY_REG(PWR->CR2, PWR_CR2_PVDFT, PVDLowLevel);
645}
646
647/**
648  * @brief  Get the low voltage threshold detection
649  * @rmtoll CR2          PLS           LL_PWR_GetPVDLowLevel
650  * @retval Returned value can be one of the following values:
651  *         @arg @ref LL_PWR_PVDLLEVEL_0
652  *         @arg @ref LL_PWR_PVDLLEVEL_1
653  *         @arg @ref LL_PWR_PVDLLEVEL_2
654  *         @arg @ref LL_PWR_PVDLLEVEL_3
655  *         @arg @ref LL_PWR_PVDLLEVEL_4
656  *         @arg @ref LL_PWR_PVDLLEVEL_5
657  *         @arg @ref LL_PWR_PVDLLEVEL_6
658  */
659__STATIC_INLINE uint32_t LL_PWR_GetPVDLowLevel(void)
660{
661  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDFT));
662}
663
664/**
665  * @brief  Enable Power Voltage Detector
666  * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
667  * @retval None
668  */
669__STATIC_INLINE void LL_PWR_EnablePVD(void)
670{
671  SET_BIT(PWR->CR2, PWR_CR2_PVDE);
672}
673
674/**
675  * @brief  Disable Power Voltage Detector
676  * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
677  * @retval None
678  */
679__STATIC_INLINE void LL_PWR_DisablePVD(void)
680{
681  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
682}
683
684/**
685  * @brief  Check if Power Voltage Detector is enabled
686  * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
687  * @retval State of bit (1 or 0).
688  */
689__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
690{
691  return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
692}
693#endif /* PWR_CR2_PVDE */
694
695/**
696  * @brief  Enable Internal Wake-up line
697  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
698  * @retval None
699  */
700__STATIC_INLINE void LL_PWR_EnableInternWU(void)
701{
702  SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
703}
704
705/**
706  * @brief  Disable Internal Wake-up line
707  * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
708  * @retval None
709  */
710__STATIC_INLINE void LL_PWR_DisableInternWU(void)
711{
712  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
713}
714
715/**
716  * @brief  Check if Internal Wake-up line is enabled
717  * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
718  * @retval State of bit (1 or 0).
719  */
720__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
721{
722  return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
723}
724
725/**
726  * @brief  Enable pull-up and pull-down configuration
727  * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
728  * @retval None
729  */
730__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
731{
732  SET_BIT(PWR->CR3, PWR_CR3_APC);
733}
734
735/**
736  * @brief  Disable pull-up and pull-down configuration
737  * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
738  * @retval None
739  */
740__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
741{
742  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
743}
744
745/**
746  * @brief  Check if pull-up and pull-down configuration  is enabled
747  * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
748  * @retval State of bit (1 or 0).
749  */
750__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
751{
752  return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
753}
754
755#if defined(PWR_CR3_RRS)
756/**
757  * @brief  Enable SRAM content retention in Standby mode
758  * @rmtoll CR3          RRS           LL_PWR_EnableSRAMRetention
759  * @retval None
760  */
761__STATIC_INLINE void LL_PWR_EnableSRAMRetention(void)
762{
763  SET_BIT(PWR->CR3, PWR_CR3_RRS);
764}
765
766/**
767  * @brief  Disable SRAM content retention in Standby mode
768  * @rmtoll CR3          RRS           LL_PWR_DisableSRAMRetention
769  * @retval None
770  */
771__STATIC_INLINE void LL_PWR_DisableSRAMRetention(void)
772{
773  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
774}
775
776/**
777  * @brief  Check if SRAM content retention in Standby mode is enabled
778  * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAMRetention
779  * @retval State of bit (1 or 0).
780  */
781__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void)
782{
783  return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
784}
785#endif /* PWR_CR3_RRS */
786
787#if defined(PWR_CR3_ENB_ULP)
788/**
789  * @brief  Enable sampling mode of LPMMU reset block
790  * @rmtoll CR3          ENB_ULP       LL_PWR_EnableLPMUResetSamplingMode
791  * @retval None
792  */
793__STATIC_INLINE void LL_PWR_EnableLPMUResetSamplingMode(void)
794{
795  SET_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
796}
797
798/**
799  * @brief  Disable sampling mode of LPMMU reset block
800  * @rmtoll CR3          ENB_ULP       LL_PWR_DisableLPMUResetSamplingMode
801  * @retval None
802  */
803__STATIC_INLINE void LL_PWR_DisableLPMUResetSamplingMode(void)
804{
805  CLEAR_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
806}
807
808/**
809  * @brief  Check if sampling mode of LPMMU reset block
810  * @rmtoll CR3          ENB_ULP       LL_PWR_IsEnableLPMUResetSamplingMode
811  * @retval State of bit (1 or 0).
812  */
813__STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode(void)
814{
815  return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL);
816}
817#endif /* PWR_CR3_ENB_ULP */
818
819/**
820  * @brief  Enable the WakeUp PINx functionality
821  * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
822  *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
823  *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
824  *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
825  *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
826  *         CR3          EWUP6         LL_PWR_EnableWakeUpPin
827  * @param  WakeUpPin This parameter can be one of the following values:
828  *         @arg @ref LL_PWR_WAKEUP_PIN1
829  *         @arg @ref LL_PWR_WAKEUP_PIN2
830  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
831  *         @arg @ref LL_PWR_WAKEUP_PIN4
832  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
833  *         @arg @ref LL_PWR_WAKEUP_PIN6
834  * @retval None
835  * @note (*) availability depends on devices
836  */
837__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
838{
839  SET_BIT(PWR->CR3, WakeUpPin);
840}
841
842/**
843  * @brief  Disable the WakeUp PINx functionality
844  * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
845  *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
846  *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
847  *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
848  *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
849  *         CR3          EWUP6         LL_PWR_DisableWakeUpPin
850  * @param  WakeUpPin This parameter can be one of the following values:
851  *         @arg @ref LL_PWR_WAKEUP_PIN1
852  *         @arg @ref LL_PWR_WAKEUP_PIN2
853  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
854  *         @arg @ref LL_PWR_WAKEUP_PIN4
855  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
856  *         @arg @ref LL_PWR_WAKEUP_PIN6
857  * @retval None
858  * @note (*) availability depends on devices
859  */
860__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
861{
862  CLEAR_BIT(PWR->CR3, WakeUpPin);
863}
864
865/**
866  * @brief  Check if the WakeUp PINx functionality is enabled
867  * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
868  *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
869  *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
870  *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
871  *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
872  *         CR3          EWUP6         LL_PWR_IsEnabledWakeUpPin
873  * @param  WakeUpPin This parameter can be one of the following values:
874  *         @arg @ref LL_PWR_WAKEUP_PIN1
875  *         @arg @ref LL_PWR_WAKEUP_PIN2
876  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
877  *         @arg @ref LL_PWR_WAKEUP_PIN4
878  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
879  *         @arg @ref LL_PWR_WAKEUP_PIN6
880  * @retval State of bit (1 or 0).
881  * @note (*) availability depends on devices
882  */
883__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
884{
885  return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
886}
887
888/**
889  * @brief  Set the resistor impedance
890  * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
891  * @param  Resistor This parameter can be one of the following values:
892  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
893  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
894  * @retval None
895  */
896__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
897{
898  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
899}
900
901/**
902  * @brief  Get the resistor impedance
903  * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
904  * @retval Returned value can be one of the following values:
905  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
906  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
907  */
908__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
909{
910  return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
911}
912
913/**
914  * @brief  Enable battery charging
915  * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
916  * @retval None
917  */
918__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
919{
920  SET_BIT(PWR->CR4, PWR_CR4_VBE);
921}
922
923/**
924  * @brief  Disable battery charging
925  * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
926  * @retval None
927  */
928__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
929{
930  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
931}
932
933/**
934  * @brief  Check if battery charging is enabled
935  * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
936  * @retval State of bit (1 or 0).
937  */
938__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
939{
940  return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
941}
942
943/**
944  * @brief  Set the Wake-Up pin polarity low for the event detection
945  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
946  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
947  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
948  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
949  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow\n
950  *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityLow
951  * @param  WakeUpPin This parameter can be one of the following values:
952  *         @arg @ref LL_PWR_WAKEUP_PIN1
953  *         @arg @ref LL_PWR_WAKEUP_PIN2
954  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
955  *         @arg @ref LL_PWR_WAKEUP_PIN4
956  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
957  *         @arg @ref LL_PWR_WAKEUP_PIN6
958  * @retval None
959  * @note (*) availability depends on devices
960  */
961__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
962{
963  SET_BIT(PWR->CR4, WakeUpPin);
964}
965
966/**
967  * @brief  Set the Wake-Up pin polarity high for the event detection
968  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
969  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
970  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
971  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
972  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh\n
973  *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityHigh
974  * @param  WakeUpPin This parameter can be one of the following values:
975  *         @arg @ref LL_PWR_WAKEUP_PIN1
976  *         @arg @ref LL_PWR_WAKEUP_PIN2
977  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
978  *         @arg @ref LL_PWR_WAKEUP_PIN4
979  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
980  *         @arg @ref LL_PWR_WAKEUP_PIN6
981  * @note (*) availability depends on devices
982  * @retval None
983  */
984__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
985{
986  CLEAR_BIT(PWR->CR4, WakeUpPin);
987}
988
989/**
990  * @brief  Get the Wake-Up pin polarity for the event detection
991  * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
992  *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
993  *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
994  *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
995  *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow\n
996  *         CR4          WP6           LL_PWR_IsWakeUpPinPolarityLow
997  * @param  WakeUpPin This parameter can be one of the following values:
998  *         @arg @ref LL_PWR_WAKEUP_PIN1
999  *         @arg @ref LL_PWR_WAKEUP_PIN2
1000  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1001  *         @arg @ref LL_PWR_WAKEUP_PIN4
1002  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1003  *         @arg @ref LL_PWR_WAKEUP_PIN6
1004  * @note (*) availability depends on devices
1005  * @retval State of bit (1 or 0).
1006  */
1007__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1008{
1009  return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1010}
1011
1012/**
1013  * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
1014  * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
1015  *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
1016  *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
1017  *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
1018  *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
1019  *         PUCRF        PU0-13        LL_PWR_EnableGPIOPullUp
1020  * @param  GPIO This parameter can be one of the following values:
1021  *         @arg @ref LL_PWR_GPIO_A
1022  *         @arg @ref LL_PWR_GPIO_B
1023  *         @arg @ref LL_PWR_GPIO_C
1024  *         @arg @ref LL_PWR_GPIO_D
1025  *         @arg @ref LL_PWR_GPIO_E (*)
1026  *         @arg @ref LL_PWR_GPIO_F
1027  * @param  GPIONumber This parameter can be one of the following values:
1028  *         @arg @ref LL_PWR_GPIO_BIT_0
1029  *         @arg @ref LL_PWR_GPIO_BIT_1
1030  *         @arg @ref LL_PWR_GPIO_BIT_2
1031  *         @arg @ref LL_PWR_GPIO_BIT_3
1032  *         @arg @ref LL_PWR_GPIO_BIT_4
1033  *         @arg @ref LL_PWR_GPIO_BIT_5
1034  *         @arg @ref LL_PWR_GPIO_BIT_6
1035  *         @arg @ref LL_PWR_GPIO_BIT_7
1036  *         @arg @ref LL_PWR_GPIO_BIT_8
1037  *         @arg @ref LL_PWR_GPIO_BIT_9
1038  *         @arg @ref LL_PWR_GPIO_BIT_10
1039  *         @arg @ref LL_PWR_GPIO_BIT_11
1040  *         @arg @ref LL_PWR_GPIO_BIT_12
1041  *         @arg @ref LL_PWR_GPIO_BIT_13
1042  *         @arg @ref LL_PWR_GPIO_BIT_14
1043  *         @arg @ref LL_PWR_GPIO_BIT_15
1044  * @retval None
1045  */
1046__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1047{
1048  SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1049}
1050
1051/**
1052  * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
1053  * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
1054  *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
1055  *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
1056  *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
1057  *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
1058  *         PUCRF        PU0-13        LL_PWR_DisableGPIOPullUp
1059  * @param  GPIO This parameter can be one of the following values:
1060  *         @arg @ref LL_PWR_GPIO_A
1061  *         @arg @ref LL_PWR_GPIO_B
1062  *         @arg @ref LL_PWR_GPIO_C
1063  *         @arg @ref LL_PWR_GPIO_D
1064  *         @arg @ref LL_PWR_GPIO_E (*)
1065  *         @arg @ref LL_PWR_GPIO_F
1066  * @param  GPIONumber This parameter can be one of the following values:
1067  *         @arg @ref LL_PWR_GPIO_BIT_0
1068  *         @arg @ref LL_PWR_GPIO_BIT_1
1069  *         @arg @ref LL_PWR_GPIO_BIT_2
1070  *         @arg @ref LL_PWR_GPIO_BIT_3
1071  *         @arg @ref LL_PWR_GPIO_BIT_4
1072  *         @arg @ref LL_PWR_GPIO_BIT_5
1073  *         @arg @ref LL_PWR_GPIO_BIT_6
1074  *         @arg @ref LL_PWR_GPIO_BIT_7
1075  *         @arg @ref LL_PWR_GPIO_BIT_8
1076  *         @arg @ref LL_PWR_GPIO_BIT_9
1077  *         @arg @ref LL_PWR_GPIO_BIT_10
1078  *         @arg @ref LL_PWR_GPIO_BIT_11
1079  *         @arg @ref LL_PWR_GPIO_BIT_12
1080  *         @arg @ref LL_PWR_GPIO_BIT_13
1081  *         @arg @ref LL_PWR_GPIO_BIT_14
1082  *         @arg @ref LL_PWR_GPIO_BIT_15
1083  * @retval None
1084  */
1085__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1086{
1087  CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1088}
1089
1090/**
1091  * @brief  Check if GPIO pull-up state is enabled
1092  * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
1093  *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
1094  *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
1095  *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
1096  *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
1097  *         PUCRF        PU0-13        LL_PWR_IsEnabledGPIOPullUp
1098  * @param  GPIO This parameter can be one of the following values:
1099  *         @arg @ref LL_PWR_GPIO_A
1100  *         @arg @ref LL_PWR_GPIO_B
1101  *         @arg @ref LL_PWR_GPIO_C
1102  *         @arg @ref LL_PWR_GPIO_D
1103  *         @arg @ref LL_PWR_GPIO_E (*)
1104  *         @arg @ref LL_PWR_GPIO_F
1105  * @param  GPIONumber This parameter can be one of the following values:
1106  *         @arg @ref LL_PWR_GPIO_BIT_0
1107  *         @arg @ref LL_PWR_GPIO_BIT_1
1108  *         @arg @ref LL_PWR_GPIO_BIT_2
1109  *         @arg @ref LL_PWR_GPIO_BIT_3
1110  *         @arg @ref LL_PWR_GPIO_BIT_4
1111  *         @arg @ref LL_PWR_GPIO_BIT_5
1112  *         @arg @ref LL_PWR_GPIO_BIT_6
1113  *         @arg @ref LL_PWR_GPIO_BIT_7
1114  *         @arg @ref LL_PWR_GPIO_BIT_8
1115  *         @arg @ref LL_PWR_GPIO_BIT_9
1116  *         @arg @ref LL_PWR_GPIO_BIT_10
1117  *         @arg @ref LL_PWR_GPIO_BIT_11
1118  *         @arg @ref LL_PWR_GPIO_BIT_12
1119  *         @arg @ref LL_PWR_GPIO_BIT_13
1120  *         @arg @ref LL_PWR_GPIO_BIT_14
1121  *         @arg @ref LL_PWR_GPIO_BIT_15
1122  * @retval State of bit (1 or 0).
1123  */
1124__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1125{
1126  return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1127}
1128
1129/**
1130  * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
1131  * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
1132  *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
1133  *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
1134  *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
1135  *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
1136  *         PDCRF        PD0-13        LL_PWR_EnableGPIOPullDown
1137  * @param  GPIO This parameter can be one of the following values:
1138  *         @arg @ref LL_PWR_GPIO_A
1139  *         @arg @ref LL_PWR_GPIO_B
1140  *         @arg @ref LL_PWR_GPIO_C
1141  *         @arg @ref LL_PWR_GPIO_D
1142  *         @arg @ref LL_PWR_GPIO_E (*)
1143  *         @arg @ref LL_PWR_GPIO_F
1144  * @param  GPIONumber This parameter can be one of the following values:
1145  *         @arg @ref LL_PWR_GPIO_BIT_0
1146  *         @arg @ref LL_PWR_GPIO_BIT_1
1147  *         @arg @ref LL_PWR_GPIO_BIT_2
1148  *         @arg @ref LL_PWR_GPIO_BIT_3
1149  *         @arg @ref LL_PWR_GPIO_BIT_4
1150  *         @arg @ref LL_PWR_GPIO_BIT_5
1151  *         @arg @ref LL_PWR_GPIO_BIT_6
1152  *         @arg @ref LL_PWR_GPIO_BIT_7
1153  *         @arg @ref LL_PWR_GPIO_BIT_8
1154  *         @arg @ref LL_PWR_GPIO_BIT_9
1155  *         @arg @ref LL_PWR_GPIO_BIT_10
1156  *         @arg @ref LL_PWR_GPIO_BIT_11
1157  *         @arg @ref LL_PWR_GPIO_BIT_12
1158  *         @arg @ref LL_PWR_GPIO_BIT_13
1159  *         @arg @ref LL_PWR_GPIO_BIT_14
1160  *         @arg @ref LL_PWR_GPIO_BIT_15
1161  * @retval None
1162  */
1163__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1164{
1165  SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1166}
1167
1168/**
1169  * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
1170  * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
1171  *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
1172  *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
1173  *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
1174  *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
1175  *         PDCRF        PD0-13        LL_PWR_DisableGPIOPullDown
1176  * @param  GPIO This parameter can be one of the following values:
1177  *         @arg @ref LL_PWR_GPIO_A
1178  *         @arg @ref LL_PWR_GPIO_B
1179  *         @arg @ref LL_PWR_GPIO_C
1180  *         @arg @ref LL_PWR_GPIO_D
1181  *         @arg @ref LL_PWR_GPIO_E (*)
1182  *         @arg @ref LL_PWR_GPIO_F
1183  * @param  GPIONumber This parameter can be one of the following values:
1184  *         @arg @ref LL_PWR_GPIO_BIT_0
1185  *         @arg @ref LL_PWR_GPIO_BIT_1
1186  *         @arg @ref LL_PWR_GPIO_BIT_2
1187  *         @arg @ref LL_PWR_GPIO_BIT_3
1188  *         @arg @ref LL_PWR_GPIO_BIT_4
1189  *         @arg @ref LL_PWR_GPIO_BIT_5
1190  *         @arg @ref LL_PWR_GPIO_BIT_6
1191  *         @arg @ref LL_PWR_GPIO_BIT_7
1192  *         @arg @ref LL_PWR_GPIO_BIT_8
1193  *         @arg @ref LL_PWR_GPIO_BIT_9
1194  *         @arg @ref LL_PWR_GPIO_BIT_10
1195  *         @arg @ref LL_PWR_GPIO_BIT_11
1196  *         @arg @ref LL_PWR_GPIO_BIT_12
1197  *         @arg @ref LL_PWR_GPIO_BIT_13
1198  *         @arg @ref LL_PWR_GPIO_BIT_14
1199  *         @arg @ref LL_PWR_GPIO_BIT_15
1200  * @retval None
1201  */
1202__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1203{
1204  CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1205}
1206
1207/**
1208  * @brief  Check if GPIO pull-down state is enabled
1209  * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
1210  *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
1211  *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
1212  *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
1213  *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
1214  *         PDCRF        PD0-13        LL_PWR_IsEnabledGPIOPullDown
1215  * @param  GPIO This parameter can be one of the following values:
1216  *         @arg @ref LL_PWR_GPIO_A
1217  *         @arg @ref LL_PWR_GPIO_B
1218  *         @arg @ref LL_PWR_GPIO_C
1219  *         @arg @ref LL_PWR_GPIO_D
1220  *         @arg @ref LL_PWR_GPIO_E (*)
1221  *         @arg @ref LL_PWR_GPIO_F
1222  * @param  GPIONumber This parameter can be one of the following values:
1223  *         @arg @ref LL_PWR_GPIO_BIT_0
1224  *         @arg @ref LL_PWR_GPIO_BIT_1
1225  *         @arg @ref LL_PWR_GPIO_BIT_2
1226  *         @arg @ref LL_PWR_GPIO_BIT_3
1227  *         @arg @ref LL_PWR_GPIO_BIT_4
1228  *         @arg @ref LL_PWR_GPIO_BIT_5
1229  *         @arg @ref LL_PWR_GPIO_BIT_6
1230  *         @arg @ref LL_PWR_GPIO_BIT_7
1231  *         @arg @ref LL_PWR_GPIO_BIT_8
1232  *         @arg @ref LL_PWR_GPIO_BIT_9
1233  *         @arg @ref LL_PWR_GPIO_BIT_10
1234  *         @arg @ref LL_PWR_GPIO_BIT_11
1235  *         @arg @ref LL_PWR_GPIO_BIT_12
1236  *         @arg @ref LL_PWR_GPIO_BIT_13
1237  *         @arg @ref LL_PWR_GPIO_BIT_14
1238  *         @arg @ref LL_PWR_GPIO_BIT_15
1239  * @retval State of bit (1 or 0).
1240  */
1241__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1242{
1243  return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1244}
1245
1246/**
1247  * @}
1248  */
1249
1250/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1251  * @{
1252  */
1253
1254/**
1255  * @brief  Get Internal Wake-up line Flag
1256  * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
1257  * @retval State of bit (1 or 0).
1258  */
1259__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1260{
1261  return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1262}
1263
1264/**
1265  * @brief  Get Stand-By Flag
1266  * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
1267  * @retval State of bit (1 or 0).
1268  */
1269__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1270{
1271  return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1272}
1273
1274/**
1275  * @brief  Get Wake-up Flag 6
1276  * @rmtoll SR1          WUF6          LL_PWR_IsActiveFlag_WU6
1277  * @retval State of bit (1 or 0).
1278  */
1279__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1280{
1281  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
1282}
1283
1284#if defined(PWR_CR3_EWUP5)
1285/**
1286  * @brief  Get Wake-up Flag 5
1287  * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
1288  * @retval State of bit (1 or 0).
1289  */
1290__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1291{
1292  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1293}
1294#endif /* PWR_CR3_EWUP5 */
1295
1296/**
1297  * @brief  Get Wake-up Flag 4
1298  * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
1299  * @retval State of bit (1 or 0).
1300  */
1301__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1302{
1303  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1304}
1305
1306#if defined(PWR_CR3_EWUP3)
1307/**
1308  * @brief  Get Wake-up Flag 3
1309  * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
1310  * @retval State of bit (1 or 0).
1311  */
1312__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1313{
1314  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1315}
1316#endif /* PWR_CR3_EWUP3 */
1317
1318/**
1319  * @brief  Get Wake-up Flag 2
1320  * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
1321  * @retval State of bit (1 or 0).
1322  */
1323__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1324{
1325  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1326}
1327
1328/**
1329  * @brief  Get Wake-up Flag 1
1330  * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
1331  * @retval State of bit (1 or 0).
1332  */
1333__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1334{
1335  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1336}
1337
1338/**
1339  * @brief  Clear Stand-By Flag
1340  * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
1341  * @retval None
1342  */
1343__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1344{
1345  WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1346}
1347
1348/**
1349  * @brief  Clear Wake-up Flags
1350  * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
1351  * @retval None
1352  */
1353__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1354{
1355  WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1356}
1357
1358/**
1359  * @brief  Clear Wake-up Flag 6
1360  * @rmtoll SCR          CWUF6         LL_PWR_ClearFlag_WU6
1361  * @retval None
1362  */
1363__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1364{
1365  WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
1366}
1367
1368#if defined(PWR_CR3_EWUP5)
1369/**
1370  * @brief  Clear Wake-up Flag 5
1371  * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
1372  * @retval None
1373  */
1374__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1375{
1376  WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1377}
1378#endif /* PWR_CR3_EWUP5 */
1379
1380/**
1381  * @brief  Clear Wake-up Flag 4
1382  * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
1383  * @retval None
1384  */
1385__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1386{
1387  WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1388}
1389
1390#if defined(PWR_CR3_EWUP3)
1391/**
1392  * @brief  Clear Wake-up Flag 3
1393  * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
1394  * @retval None
1395  */
1396__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1397{
1398  WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1399}
1400#endif /* PWR_CR3_EWUP3 */
1401
1402/**
1403  * @brief  Clear Wake-up Flag 2
1404  * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
1405  * @retval None
1406  */
1407__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1408{
1409  WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1410}
1411
1412/**
1413  * @brief  Clear Wake-up Flag 1
1414  * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
1415  * @retval None
1416  */
1417__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1418{
1419  WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1420}
1421
1422#if defined (PWR_PVM_SUPPORT)
1423/**
1424  * @brief  Indicate whether VDD voltage is below or above the selected PVD
1425  *         threshold
1426  * @rmtoll SR2          PVDMO_USB          LL_PWR_IsActiveFlag_PVMOUSB
1427  * @retval State of bit (1 or 0).
1428  */
1429__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void)
1430{
1431  return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL);
1432}
1433#endif /* PWR_PVM_SUPPORT */
1434
1435#if defined(PWR_SR2_PVDO)
1436/**
1437  * @brief  Indicate whether VDD voltage is below or above the selected PVD
1438  *         threshold
1439  * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
1440  * @retval State of bit (1 or 0).
1441  */
1442__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1443{
1444  return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1445}
1446#endif /* PWR_SR2_PVDO */
1447
1448/**
1449  * @brief  Indicate whether the regulator is ready in the selected voltage
1450  *         range or if its output voltage is still changing to the required
1451  *         voltage level
1452  * @note:  Take care, return value "0" means the regulator is ready.
1453  *         Return value "1" means the output voltage range is still changing.
1454  * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
1455  * @retval State of bit (1 or 0).
1456  */
1457__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1458{
1459  return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1460}
1461
1462/**
1463  * @brief  Indicate whether the regulator is ready in main mode or is in
1464  *         low-power mode
1465  * @note:  Take care, return value "0" means regulator is ready in main mode
1466  *         Return value "1" means regulator is in low-power mode (LPR)
1467  * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
1468  * @retval State of bit (1 or 0).
1469  */
1470__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1471{
1472  return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1473}
1474
1475/**
1476  * @brief  Indicate whether or not the low-power regulator is ready
1477  * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
1478  * @retval State of bit (1 or 0).
1479  */
1480__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1481{
1482  return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1483}
1484
1485/**
1486  * @brief  Indicate whether or not the flash is ready to be accessed
1487  * @rmtoll SR2          FLASH_RDY     LL_PWR_IsActiveFlag_FLASH_RDY
1488  * @retval State of bit (1 or 0).
1489  */
1490__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
1491{
1492  return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
1493}
1494
1495
1496/**
1497  * @}
1498  */
1499
1500#if defined(USE_FULL_LL_DRIVER)
1501/** @defgroup PWR_LL_EF_Init De-initialization function
1502  * @{
1503  */
1504ErrorStatus LL_PWR_DeInit(void);
1505/**
1506  * @}
1507  */
1508#endif /* USE_FULL_LL_DRIVER */
1509
1510/**
1511  * @}
1512  */
1513
1514/**
1515  * @}
1516  */
1517
1518#endif /* defined(PWR) */
1519
1520/**
1521  * @}
1522  */
1523
1524#ifdef __cplusplus
1525}
1526#endif
1527
1528#endif /* STM32G0xx_LL_PWR_H */
Note: See TracBrowser for help on using the repository browser.