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stm32g0xx_ll_system.h

Last change on this file was 6, checked in by f.jahn, 3 months ago

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_system.h
4	* @author MCD Application Team
5	* @brief Header file of SYSTEM LL module.
6	*
7	******************************************************************************
8	* @attention
9	*
10	* Copyright (c) 2018 STMicroelectronics.
11	* All rights reserved.
12	*
13	* This software is licensed under terms that can be found in the LICENSE file
14	* in the root directory of this software component.
15	* If no LICENSE file comes with this software, it is provided AS-IS.
16	*
17	******************************************************************************
18	@verbatim
19	==============================================================================
20	##### How to use this driver #####
21	==============================================================================
22	[..]
23	The LL SYSTEM driver contains a set of generic APIs that can be
24	used by user:
25	(+) Some of the FLASH features need to be handled in the SYSTEM file.
26	(+) Access to DBG registers
27	(+) Access to SYSCFG registers
28	(+) Access to VREFBUF registers
29
30	@endverbatim
31	******************************************************************************
32	*/
33
34	/* Define to prevent recursive inclusion -------------------------------------*/
35	#ifndef STM32G0xx_LL_SYSTEM_H
36	#define STM32G0xx_LL_SYSTEM_H
37
38	#ifdef __cplusplus
39	extern "C" {
40	#endif
41
42	/* Includes ------------------------------------------------------------------*/
43	#include "stm32g0xx.h"
44
45	/** @addtogroup STM32G0xx_LL_Driver
46	* @{
47	*/
48
49	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBG)
50
51	/** @defgroup SYSTEM_LL SYSTEM
52	* @{
53	*/
54
55	/* Private types -------------------------------------------------------------*/
56	/* Private variables ---------------------------------------------------------*/
57
58	/* Private constants ---------------------------------------------------------*/
59	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
60	* @{
61	*/
62
63	/**
64	* @}
65	*/
66
67	/* Private macros ------------------------------------------------------------*/
68
69	/* Exported types ------------------------------------------------------------*/
70	/* Exported constants --------------------------------------------------------*/
71	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
72	* @{
73	*/
74
75	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
76	* @{
77	*/
78	#define LL_SYSCFG_REMAP_FLASH 0x00000000U /!< Main Flash memory mapped at 0x00000000 /
79	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
80	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
81	/**
82	* @}
83	*/
84
85	/** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
86	* @{
87	*/
88	#define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP /!< PA11 pad behaves as PA9 pin /
89	#define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP /!< PA12 pad behaves as PA10 pin /
90	/**
91	* @}
92	*/
93
94
95	#if defined(SYSCFG_CFGR1_IR_MOD)
96	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
97	* @{
98	*/
99	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< 00: Timer16 is selected as IRDA Modulation envelope source /
100	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< 01: USART1 is selected as IRDA Modulation envelope source /
101	#if defined(USART4)
102	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< 10: USART4 is selected as IRDA Modulation envelope source /
103	#else
104	#define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /!< 10: USART2 is selected as IRDA Modulation envelope source /
105	#endif /* USART4 */
106	/**
107	* @}
108	*/
109	/** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
110	* @{
111	*/
112	#define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U /!< 0: Output of IRDA (IROut) not inverted /
113	#define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL) /!< 1: Output of IRDA (IROut) inverted /
114	/**
115	* @}
116	*/
117	#endif /* SYSCFG_CFGR1_IR_MOD */
118
119	#if defined(SYSCFG_CFGR1_BOOSTEN)
120	/** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable
121	* @{
122	*/
123	#define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN /!< I/O analog switch voltage booster enable /
124	/**
125	* @}
126	*/
127	#endif /* SYSCFG_CFGR1_BOOSTEN */
128
129	#if defined(SYSCFG_CFGR1_UCPD1_STROBE) \|\| defined(SYSCFG_CFGR1_UCPD2_STROBE)
130	/** @defgroup SYSTEM_LL_EC_UCPD_DBATTDIS SYSCFG UCPD Dead Battery feature Disable
131	* @{
132	*/
133	#define LL_SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /!< UCPD1 STROBE sw configuration /
134	#define LL_SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /!< UCPD2 STROBE sw configuration /
135	/**
136	* @}
137	*/
138	#endif /* SYSCFG_CFGR1_UCPD1_STROBE) \|\| SYSCFG_CFGR1_UCPD2_STROBE */
139
140	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
141	* @{
142	*/
143	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< I2C PB6 Fast mode plus /
144	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< I2C PB7 Fast mode plus /
145	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< I2C PB8 Fast mode plus /
146	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< I2C PB9 Fast mode plus /
147	#if defined(SYSCFG_CFGR1_I2C1_FMP)
148	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< Enable I2C1 Fast mode Plus /
149	#endif /SYSCFG_CFGR1_I2C1_FMP/
150	#if defined(SYSCFG_CFGR1_I2C2_FMP)
151	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< Enable I2C2 Fast mode plus /
152	#endif /SYSCFG_CFGR1_I2C2_FMP/
153	#if defined(SYSCFG_CFGR1_I2C_PA9_FMP)
154	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /!< Enable Fast Mode Plus on PA9 /
155	#endif /SYSCFG_CFGR1_I2C_PA9_FMP/
156	#if defined(SYSCFG_CFGR1_I2C_PA10_FMP)
157	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /!< Enable Fast Mode Plus on PA10 /
158	#endif /SYSCFG_CFGR1_I2C_PA10_FMP/
159	#if defined(STM32G0C1xx) \|\| defined(STM32G0B1xx) \|\| defined(STM32G0B0xx)
160	#if defined(SYSCFG_CFGR1_I2C3_FMP)
161	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< Enable I2C3 Fast mode plus /
162	#endif /SYSCFG_CFGR1_I2C3_FMP/
163	#endif /* STM32G0C1xx \|\| STM32G0B1xx \|\| STM32G0B0xx */
164	/**
165	* @}
166	*/
167
168	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
169	* @{
170	*/
171	#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
172	with Break Input of TIM1/15/16/17 */
173	#if defined (PWR_PVD_SUPPORT)
174	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
175	with TIM1/15/16/17 Break Input and also
176	the PVDE and PLS bits of the Power Control Interface */
177	#endif /* PWR_PVD_SUPPORT */
178	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal
179	with Break Input of TIM1/15/16/17 */
180	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of
181	CortexM0 with Break Input of TIM1/15/16/17 */
182	/**
183	* @}
184	*/
185
186	#if defined(SYSCFG_CDEN_SUPPORT)
187	/** @defgroup SYSTEM_LL_EC_CLAMPING_DIODE SYSCFG CLAMPING DIODE
188	* @{
189	*/
190	#define LL_SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN /!< Enables Clamping diode of PA1 /
191	#define LL_SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN /!< Enables Clamping diode of PA3 /
192	#define LL_SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN /!< Enables Clamping diode of PA5 /
193	#define LL_SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN /!< Enables Clamping diode of PA6 /
194	#define LL_SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN /!< Enables Clamping diode of PA13 /
195	#define LL_SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN /!< Enables Clamping diode of PB0 /
196	#define LL_SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN /!< Enables Clamping diode of PB1 /
197	#define LL_SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN /!< Enables Clamping diode of PB2 /
198	/**
199	* @}
200	*/
201	#endif /* SYSCFG_CDEN_SUPPORT */
202
203	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
204	* @{
205	*/
206	#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
207	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
208	#endif /DBG_APB_FZ1_DBG_TIM2_STOP/
209	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
210	#if defined(STM32G0C1xx) \|\| defined(STM32G0B1xx) \|\| defined(STM32G0B0xx)
211	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBG_APB_FZ1_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
212	#endif /* STM32G0C1xx \|\| STM32G0B1xx \|\| STM32G0B0xx */
213	#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
214	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
215	#endif /DBG_APB_FZ1_DBG_TIM6_STOP/
216	#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
217	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
218	#endif /DBG_APB_FZ1_DBG_TIM7_STOP/
219	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
220	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
221	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
222	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /!< I2C1 SMBUS timeout mode stopped when Core is halted /
223	#if defined(STM32G0C1xx) \|\| defined(STM32G0B1xx) \|\| defined(STM32G0B0xx)
224	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP /!< I2C2 SMBUS timeout mode stopped when Core is halted /
225	#endif /* STM32G0C1xx \|\| STM32G0B1xx \|\| STM32G0B0xx */
226	#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
227	#define LL_DBGMCU_APB1_GRP1_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP /!< LPTIM2 counter stopped when Core is halted /
228	#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
229	#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
230	#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP /!< LPTIM1 counter stopped when Core is halted /
231	#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
232	/**
233	* @}
234	*/
235
236	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
237	* @{
238	*/
239	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
240	#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
241	#define LL_DBGMCU_APB2_GRP1_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
242	#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
243	#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
244	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
245	#endif /DBG_APB_FZ2_DBG_TIM15_STOP/
246	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
247	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
248	/**
249	* @}
250	*/
251
252
253	#if defined(VREFBUF)
254	/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
255	* @{
256	*/
257	#define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /!< Voltage reference scale 0 (VREF_OUT1) /
258	#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /!< Voltage reference scale 1 (VREF_OUT2) /
259	/**
260	* @}
261	*/
262	#endif /* VREFBUF */
263
264	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
265	* @{
266	*/
267	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
268	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /!< FLASH One Latency cycle /
269	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /!< FLASH Two wait states /
270	#define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 \| FLASH_ACR_LATENCY_0) /!< FLASH Three wait states /
271	/**
272	* @}
273	*/
274
275	/**
276	* @}
277	*/
278
279	/* Exported macro ------------------------------------------------------------*/
280
281	/* Exported functions --------------------------------------------------------*/
282	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
283	* @{
284	*/
285
286	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
287	* @{
288	*/
289
290	/**
291	* @brief Set memory mapping at address 0x00000000
292	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
293	* @param Memory This parameter can be one of the following values:
294	* @arg @ref LL_SYSCFG_REMAP_FLASH
295	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
296	* @arg @ref LL_SYSCFG_REMAP_SRAM
297	* @retval None
298	*/
299	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
300	{
301	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
302	}
303
304	/**
305	* @brief Get memory mapping at address 0x00000000
306	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
307	* @retval Returned value can be one of the following values:
308	* @arg @ref LL_SYSCFG_REMAP_FLASH
309	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
310	* @arg @ref LL_SYSCFG_REMAP_SRAM
311	*/
312	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
313	{
314	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
315	}
316
317	/**
318	* @brief Enable remap of a pin on different pad
319	* @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap\n
320	* SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap\n
321	* @param PinRemap This parameter can be a combination of the following values:
322	* @arg @ref LL_SYSCFG_PIN_RMP_PA11
323	* @arg @ref LL_SYSCFG_PIN_RMP_PA12
324	* @retval None
325	*/
326	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
327	{
328	SET_BIT(SYSCFG->CFGR1, PinRemap);
329	}
330
331	/**
332	* @brief Enable remap of a pin on different pad
333	* @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap\n
334	* SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap\n
335	* @param PinRemap This parameter can be a combination of the following values:
336	* @arg @ref LL_SYSCFG_PIN_RMP_PA11
337	* @arg @ref LL_SYSCFG_PIN_RMP_PA12
338	* @retval None
339	*/
340	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
341	{
342	CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
343	}
344
345	#if defined(SYSCFG_CFGR1_IR_MOD)
346	/**
347	* @brief Set IR Modulation Envelope signal source.
348	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
349	* @param Source This parameter can be one of the following values:
350	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
351	* @arg @ref LL_SYSCFG_IR_MOD_USART1
352	* @arg @ref LL_SYSCFG_IR_MOD_USART4
353	* @retval None
354	*/
355	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
356	{
357	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
358	}
359
360	/**
361	* @brief Get IR Modulation Envelope signal source.
362	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
363	* @retval Returned value can be one of the following values:
364	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
365	* @arg @ref LL_SYSCFG_IR_MOD_USART1
366	* @arg @ref LL_SYSCFG_IR_MOD_USART4
367	*/
368	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
369	{
370	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
371	}
372
373	/**
374	* @brief Set IR Output polarity.
375	* @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity
376	* @param Polarity This parameter can be one of the following values:
377	* @arg @ref LL_SYSCFG_IR_POL_INVERTED
378	* @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
379	* @retval None
380	*/
381	__STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
382	{
383	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
384	}
385
386	/**
387	* @brief Get IR Output polarity.
388	* @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity
389	* @retval Returned value can be one of the following values:
390	* @arg @ref LL_SYSCFG_IR_POL_INVERTED
391	* @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
392	*/
393	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
394	{
395	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
396	}
397	#endif /* SYSCFG_CFGR1_IR_MOD */
398
399	#if defined(SYSCFG_CFGR1_BOOSTEN)
400	/**
401	* @brief Enable I/O analog switch voltage booster.
402	* @note When voltage booster is enabled, I/O analog switches are supplied
403	* by a dedicated voltage booster, from VDD power domain. This is
404	* the recommended configuration with low VDDA voltage operation.
405	* @note The I/O analog switch voltage booster is relevant for peripherals
406	* using I/O in analog input: ADC, COMP.
407	* However, COMP and OPAMP inputs have a high impedance and
408	* voltage booster do not impact performance significantly.
409	* Therefore, the voltage booster is mainly intended for
410	* usage with ADC.
411	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
412	* @retval None
413	*/
414	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
415	{
416	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
417	}
418
419	/**
420	* @brief Disable I/O analog switch voltage booster.
421	* @note When voltage booster is enabled, I/O analog switches are supplied
422	* by a dedicated voltage booster, from VDD power domain. This is
423	* the recommended configuration with low VDDA voltage operation.
424	* @note The I/O analog switch voltage booster is relevant for peripherals
425	* using I/O in analog input: ADC, COMP.
426	* However, COMP and OPAMP inputs have a high impedance and
427	* voltage booster do not impact performance significantly.
428	* Therefore, the voltage booster is mainly intended for
429	* usage with ADC.
430	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
431	* @retval None
432	*/
433	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
434	{
435	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
436	}
437	#endif /* SYSCFG_CFGR1_BOOSTEN */
438
439	/**
440	* @brief Enable the I2C fast mode plus driving capability.
441	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
442	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
443	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
444	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
445	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
446	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
447	* SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_EnableFastModePlus\n
448	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
449	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
450	* @param ConfigFastModePlus This parameter can be a combination of the following values:
451	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
452	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
453	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
454	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
455	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
456	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
457	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
458	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
459	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
460	*
461	* (*) value not defined in all devices
462	* @retval None
463	*/
464	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
465	{
466	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
467	}
468
469	/**
470	* @brief Disable the I2C fast mode plus driving capability.
471	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
472	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
473	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
474	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
475	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
476	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
477	* SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_DisableFastModePlus\n
478	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
479	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
480	* @param ConfigFastModePlus This parameter can be a combination of the following values:
481	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
482	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
483	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
484	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
485	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
486	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
487	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
488	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
489	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
490	*
491	* (*) value not defined in all devices
492	* @retval None
493	*/
494	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
495	{
496	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
497	}
498
499	#if defined(SYSCFG_CFGR1_UCPD1_STROBE) \|\| defined(SYSCFG_CFGR1_UCPD2_STROBE)
500	/**
501	* @brief Disable dead battery behavior
502	* @rmtoll SYSCFG_CFGR1 UCPD1_STROBE LL_SYSCFG_DisableDBATT\n
503	* SYSCFG_CFGR1 UCPD2_STROBE LL_SYSCFG_DisableDBATT
504	* @param ConfigDeadBattery This parameter can be a combination of the following values:
505	* @arg @ref LL_SYSCFG_UCPD1_STROBE\n
506	* @arg @ref LL_SYSCFG_UCPD2_STROBE
507	* (*) value not defined in all devices
508	* @retval None
509	*/
510	__STATIC_INLINE void LL_SYSCFG_DisableDBATT(uint32_t ConfigDeadBattery)
511	{
512	SET_BIT(SYSCFG->CFGR1, ConfigDeadBattery);
513	}
514	#endif /* SYSCFG_CFGR1_UCPD1_STROBE \|\| SYSCFG_CFGR1_UCPD2_STROBE */
515
516	#if defined(SYSCFG_ITLINE0_SR_EWDG)
517	/**
518	* @brief Check if Window watchdog interrupt occurred or not.
519	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
520	* @retval State of bit (1 or 0).
521	*/
522	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
523	{
524	return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)) ? 1UL : 0UL);
525	}
526	#endif /* SYSCFG_ITLINE0_SR_EWDG */
527
528	#if defined (PWR_PVD_SUPPORT)
529	/**
530	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
531	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
532	* @retval State of bit (1 or 0).
533	*/
534	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
535	{
536	return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)) ? 1UL : 0UL);
537	}
538	#endif /* PWR_PVD_SUPPORT */
539
540	#if defined (PWR_PVM_SUPPORT)
541	/**
542	* @brief Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).
543	* @rmtoll SYSCFG_ITLINE1 SR_PVMOUT LL_SYSCFG_IsActiveFlag_PVMOUT
544	* @retval State of bit (1 or 0).
545	*/
546	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT(void)
547	{
548	return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT) == (SYSCFG_ITLINE1_SR_PVMOUT)) ? 1UL : 0UL);
549	}
550	#endif /* PWR_PVM_SUPPORT */
551
552	#if defined(SYSCFG_ITLINE2_SR_RTC)
553	/**
554	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
555	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
556	* @retval State of bit (1 or 0).
557	*/
558	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
559	{
560	return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
561	}
562	#endif /* SYSCFG_ITLINE2_SR_RTC */
563
564	#if defined(SYSCFG_ITLINE2_SR_TAMPER)
565	/**
566	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
567	* @rmtoll SYSCFG_ITLINE2 SR_TAMPER LL_SYSCFG_IsActiveFlag_TAMPER
568	* @retval State of bit (1 or 0).
569	*/
570	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TAMPER(void)
571	{
572	return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_TAMPER) == (SYSCFG_ITLINE2_SR_TAMPER)) ? 1UL : 0UL);
573	}
574	#endif /* SYSCFG_ITLINE2_SR_TAMPER */
575
576	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
577	/**
578	* @brief Check if Flash interface interrupt occurred or not.
579	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
580	* @retval State of bit (1 or 0).
581	*/
582	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
583	{
584	return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
585	}
586	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
587
588	#if defined(SYSCFG_ITLINE3_SR_FLASH_ECC)
589	/**
590	* @brief Check if Flash interface interrupt occurred or not.
591	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ECC LL_SYSCFG_IsActiveFlag_FLASH_ECC
592	* @retval State of bit (1 or 0).
593	*/
594	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ECC(void)
595	{
596	return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ECC) == (SYSCFG_ITLINE3_SR_FLASH_ECC)) ? 1UL : 0UL);
597	}
598	#endif /* SYSCFG_ITLINE3_SR_FLASH_ECC */
599
600	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
601	/**
602	* @brief Check if Reset and clock control interrupt occurred or not.
603	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
604	* @retval State of bit (1 or 0).
605	*/
606	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
607	{
608	return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)) ? 1UL : 0UL);
609	}
610	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
611
612	#if defined(CRS)
613	/**
614	* @brief Check if Reset and clock control interrupt occurred or not.
615	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
616	* @retval State of bit (1 or 0).
617	*/
618	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
619	{
620	return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL);
621	}
622	#endif /* CRS */
623	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
624	/**
625	* @brief Check if EXTI line 0 interrupt occurred or not.
626	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
627	* @retval State of bit (1 or 0).
628	*/
629	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
630	{
631	return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
632	}
633	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
634
635	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
636	/**
637	* @brief Check if EXTI line 1 interrupt occurred or not.
638	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
639	* @retval State of bit (1 or 0).
640	*/
641	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
642	{
643	return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
644	}
645	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
646
647	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
648	/**
649	* @brief Check if EXTI line 2 interrupt occurred or not.
650	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
651	* @retval State of bit (1 or 0).
652	*/
653	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
654	{
655	return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
656	}
657	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
658
659	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
660	/**
661	* @brief Check if EXTI line 3 interrupt occurred or not.
662	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
663	* @retval State of bit (1 or 0).
664	*/
665	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
666	{
667	return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
668	}
669	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
670
671	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
672	/**
673	* @brief Check if EXTI line 4 interrupt occurred or not.
674	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
675	* @retval State of bit (1 or 0).
676	*/
677	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
678	{
679	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
680	}
681	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
682
683	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
684	/**
685	* @brief Check if EXTI line 5 interrupt occurred or not.
686	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
687	* @retval State of bit (1 or 0).
688	*/
689	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
690	{
691	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
692	}
693	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
694
695	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
696	/**
697	* @brief Check if EXTI line 6 interrupt occurred or not.
698	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
699	* @retval State of bit (1 or 0).
700	*/
701	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
702	{
703	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
704	}
705	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
706
707	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
708	/**
709	* @brief Check if EXTI line 7 interrupt occurred or not.
710	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
711	* @retval State of bit (1 or 0).
712	*/
713	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
714	{
715	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
716	}
717	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
718
719	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
720	/**
721	* @brief Check if EXTI line 8 interrupt occurred or not.
722	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
723	* @retval State of bit (1 or 0).
724	*/
725	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
726	{
727	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
728	}
729	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
730
731	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
732	/**
733	* @brief Check if EXTI line 9 interrupt occurred or not.
734	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
735	* @retval State of bit (1 or 0).
736	*/
737	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
738	{
739	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
740	}
741	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
742
743	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
744	/**
745	* @brief Check if EXTI line 10 interrupt occurred or not.
746	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
747	* @retval State of bit (1 or 0).
748	*/
749	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
750	{
751	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
752	}
753	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
754
755	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
756	/**
757	* @brief Check if EXTI line 11 interrupt occurred or not.
758	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
759	* @retval State of bit (1 or 0).
760	*/
761	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
762	{
763	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
764	}
765	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
766
767	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
768	/**
769	* @brief Check if EXTI line 12 interrupt occurred or not.
770	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
771	* @retval State of bit (1 or 0).
772	*/
773	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
774	{
775	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
776	}
777	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
778
779	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
780	/**
781	* @brief Check if EXTI line 13 interrupt occurred or not.
782	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
783	* @retval State of bit (1 or 0).
784	*/
785	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
786	{
787	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
788	}
789	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
790
791	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
792	/**
793	* @brief Check if EXTI line 14 interrupt occurred or not.
794	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
795	* @retval State of bit (1 or 0).
796	*/
797	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
798	{
799	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
800	}
801	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
802
803	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
804	/**
805	* @brief Check if EXTI line 15 interrupt occurred or not.
806	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
807	* @retval State of bit (1 or 0).
808	*/
809	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
810	{
811	return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
812	}
813	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
814
815	#if defined(SYSCFG_ITLINE8_SR_UCPD1)
816	/**
817	* @brief Check if UCPD1 interrupt occurred or not.
818	* @rmtoll SYSCFG_ITLINE8 SR_UCPD1 LL_SYSCFG_IsActiveFlag_UCPD1
819	* @retval State of bit (1 or 0).
820	*/
821	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD1(void)
822	{
823	return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD1) == (SYSCFG_ITLINE8_SR_UCPD1)) ? 1UL : 0UL);
824	}
825	#endif /* SYSCFG_ITLINE8_SR_UCPD1 */
826
827	#if defined(SYSCFG_ITLINE8_SR_UCPD2)
828	/**
829	* @brief Check if UCPD2 interrupt occurred or not.
830	* @rmtoll SYSCFG_ITLINE8 SR_UCPD2 LL_SYSCFG_IsActiveFlag_UCPD2
831	* @retval State of bit (1 or 0).
832	*/
833	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD2(void)
834	{
835	return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD2) == (SYSCFG_ITLINE8_SR_UCPD2)) ? 1UL : 0UL);
836	}
837	#endif /* SYSCFG_ITLINE8_SR_UCPD2 */
838
839	#if defined(SYSCFG_ITLINE8_SR_USB)
840	/**
841	* @brief Check if USB interrupt occurred or not.
842	* @rmtoll SYSCFG_ITLINE8 SR_USB LL_SYSCFG_IsActiveFlag_USB
843	* @retval State of bit (1 or 0).
844	*/
845	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void)
846	{
847	return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USB) == (SYSCFG_ITLINE8_SR_USB)) ? 1UL : 0UL);
848	}
849	#endif /* SYSCFG_ITLINE8_SR_USB */
850
851	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
852	/**
853	* @brief Check if DMA1 channel 1 interrupt occurred or not.
854	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
855	* @retval State of bit (1 or 0).
856	*/
857	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
858	{
859	return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
860	}
861	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
862
863	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
864	/**
865	* @brief Check if DMA1 channel 2 interrupt occurred or not.
866	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
867	* @retval State of bit (1 or 0).
868	*/
869	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
870	{
871	return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
872	}
873	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
874
875	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
876	/**
877	* @brief Check if DMA1 channel 3 interrupt occurred or not.
878	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
879	* @retval State of bit (1 or 0).
880	*/
881	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
882	{
883	return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
884	}
885	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
886
887	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
888	/**
889	* @brief Check if DMA1 channel 4 interrupt occurred or not.
890	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
891	* @retval State of bit (1 or 0).
892	*/
893	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
894	{
895	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL);
896	}
897	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
898
899	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
900	/**
901	* @brief Check if DMA1 channel 5 interrupt occurred or not.
902	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
903	* @retval State of bit (1 or 0).
904	*/
905	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
906	{
907	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL);
908	}
909	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
910
911	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
912	/**
913	* @brief Check if DMA1 channel 6 interrupt occurred or not.
914	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
915	* @retval State of bit (1 or 0).
916	*/
917	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
918	{
919	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL);
920	}
921	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
922
923	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
924	/**
925	* @brief Check if DMA1 channel 7 interrupt occurred or not.
926	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
927	* @retval State of bit (1 or 0).
928	*/
929	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
930	{
931	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL);
932	}
933	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
934
935	#if defined(SYSCFG_ITLINE11_SR_DMAMUX1)
936	/**
937	* @brief Check if DMAMUX interrupt occurred or not.
938	* @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX
939	* @retval State of bit (1 or 0).
940	*/
941	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
942	{
943	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL);
944	}
945	#endif /* SYSCFG_ITLINE11_SR_DMAMUX */
946
947	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH1)
948	/**
949	* @brief Check if DMA2_CH1 interrupt occurred or not.
950	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
951	* @retval State of bit (1 or 0).
952	*/
953	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
954	{
955	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH1) == (SYSCFG_ITLINE11_SR_DMA2_CH1)) ? 1UL : 0UL);
956	}
957	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH1 */
958
959	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH2)
960	/**
961	* @brief Check if DMA2_CH2 interrupt occurred or not.
962	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
963	* @retval State of bit (1 or 0).
964	*/
965	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
966	{
967	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH2) == (SYSCFG_ITLINE11_SR_DMA2_CH2)) ? 1UL : 0UL);
968	}
969	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH2 */
970
971	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
972	/**
973	* @brief Check if DMA2_CH3 interrupt occurred or not.
974	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
975	* @retval State of bit (1 or 0).
976	*/
977	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
978	{
979	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)) ? 1UL : 0UL);
980	}
981	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
982
983	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
984	/**
985	* @brief Check if DMA2_CH4 interrupt occurred or not.
986	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
987	* @retval State of bit (1 or 0).
988	*/
989	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
990	{
991	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)) ? 1UL : 0UL);
992	}
993	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
994
995	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
996	/**
997	* @brief Check if DMA2_CH5 interrupt occurred or not.
998	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
999	* @retval State of bit (1 or 0).
1000	*/
1001	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
1002	{
1003	return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)) ? 1UL : 0UL);
1004	}
1005	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
1006
1007	#if defined(SYSCFG_ITLINE12_SR_ADC)
1008	/**
1009	* @brief Check if ADC interrupt occurred or not.
1010	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
1011	* @retval State of bit (1 or 0).
1012	*/
1013	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
1014	{
1015	return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
1016	}
1017	#endif /* SYSCFG_ITLINE12_SR_ADC */
1018
1019	#if defined(SYSCFG_ITLINE12_SR_COMP1)
1020	/**
1021	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 17).
1022	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
1023	* @retval State of bit (1 or 0).
1024	*/
1025	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
1026	{
1027	return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) ? 1UL : 0UL);
1028	}
1029	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
1030
1031	#if defined(SYSCFG_ITLINE12_SR_COMP2)
1032	/**
1033	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 18).
1034	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
1035	* @retval State of bit (1 or 0).
1036	*/
1037	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
1038	{
1039	return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) ? 1UL : 0UL);
1040	}
1041	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
1042
1043	#if defined(SYSCFG_ITLINE12_SR_COMP3)
1044	/**
1045	* @brief Check if Comparator 3 interrupt occurred or not (EXTI line 20).
1046	* @rmtoll SYSCFG_ITLINE12 SR_COMP3 LL_SYSCFG_IsActiveFlag_COMP3
1047	* @retval State of bit (1 or 0).
1048	*/
1049	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP3(void)
1050	{
1051	return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP3) == (SYSCFG_ITLINE12_SR_COMP3)) ? 1UL : 0UL);
1052	}
1053	#endif /* SYSCFG_ITLINE12_SR_COMP3 */
1054
1055	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
1056	/**
1057	* @brief Check if Timer 1 break interrupt occurred or not.
1058	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
1059	* @retval State of bit (1 or 0).
1060	*/
1061	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
1062	{
1063	return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
1064	}
1065	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
1066
1067	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
1068	/**
1069	* @brief Check if Timer 1 update interrupt occurred or not.
1070	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
1071	* @retval State of bit (1 or 0).
1072	*/
1073	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
1074	{
1075	return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
1076	}
1077	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
1078
1079	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
1080	/**
1081	* @brief Check if Timer 1 trigger interrupt occurred or not.
1082	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
1083	* @retval State of bit (1 or 0).
1084	*/
1085	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
1086	{
1087	return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
1088	}
1089	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
1090
1091	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
1092	/**
1093	* @brief Check if Timer 1 commutation interrupt occurred or not.
1094	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
1095	* @retval State of bit (1 or 0).
1096	*/
1097	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
1098	{
1099	return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
1100	}
1101	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
1102
1103	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
1104	/**
1105	* @brief Check if Timer 1 capture compare interrupt occurred or not.
1106	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
1107	* @retval State of bit (1 or 0).
1108	*/
1109	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
1110	{
1111	return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL);
1112	}
1113	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
1114
1115	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
1116	/**
1117	* @brief Check if Timer 2 interrupt occurred or not.
1118	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
1119	* @retval State of bit (1 or 0).
1120	*/
1121	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
1122	{
1123	return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)) ? 1UL : 0UL);
1124	}
1125	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
1126
1127	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
1128	/**
1129	* @brief Check if Timer 3 interrupt occurred or not.
1130	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
1131	* @retval State of bit (1 or 0).
1132	*/
1133	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
1134	{
1135	return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL);
1136	}
1137	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
1138
1139	#if defined(SYSCFG_ITLINE16_SR_TIM4_GLB)
1140	/**
1141	* @brief Check if Timer 3 interrupt occurred or not.
1142	* @rmtoll SYSCFG_ITLINE16 SR_TIM4_GLB LL_SYSCFG_IsActiveFlag_TIM4
1143	* @retval State of bit (1 or 0).
1144	*/
1145	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM4(void)
1146	{
1147	return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM4_GLB) == (SYSCFG_ITLINE16_SR_TIM4_GLB)) ? 1UL : 0UL);
1148	}
1149	#endif /* SYSCFG_ITLINE16_SR_TIM4_GLB */
1150
1151	#if defined(SYSCFG_ITLINE17_SR_DAC)
1152	/**
1153	* @brief Check if DAC underrun interrupt occurred or not.
1154	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
1155	* @retval State of bit (1 or 0).
1156	*/
1157	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
1158	{
1159	return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)) ? 1UL : 0UL);
1160	}
1161	#endif /* SYSCFG_ITLINE17_SR_DAC */
1162
1163	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
1164	/**
1165	* @brief Check if Timer 6 interrupt occurred or not.
1166	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
1167	* @retval State of bit (1 or 0).
1168	*/
1169	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
1170	{
1171	return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)) ? 1UL : 0UL);
1172	}
1173	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
1174
1175	#if defined(SYSCFG_ITLINE17_SR_LPTIM1_GLB)
1176	/**
1177	* @brief Check if LPTIM1 interrupt occurred or not.
1178	* @rmtoll SYSCFG_ITLINE17 SR_LPTIM1_GLB LL_SYSCFG_IsActiveFlag_LPTIM1
1179	* @retval State of bit (1 or 0).
1180	*/
1181	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM1(void)
1182	{
1183	return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_LPTIM1_GLB) == (SYSCFG_ITLINE17_SR_LPTIM1_GLB)) ? 1UL : 0UL);
1184	}
1185	#endif /* SYSCFG_ITLINE17_SR_LPTIM1_GLB */
1186
1187	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
1188	/**
1189	* @brief Check if Timer 7 interrupt occurred or not.
1190	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
1191	* @retval State of bit (1 or 0).
1192	*/
1193	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
1194	{
1195	return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)) ? 1UL : 0UL);
1196	}
1197	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
1198
1199	#if defined(SYSCFG_ITLINE18_SR_LPTIM2_GLB)
1200	/**
1201	* @brief Check if LPTIM2 interrupt occurred or not.
1202	* @rmtoll SYSCFG_ITLINE18 SR_LPTIM2_GLB LL_SYSCFG_IsActiveFlag_LPTIM2
1203	* @retval State of bit (1 or 0).
1204	*/
1205	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM2(void)
1206	{
1207	return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_LPTIM2_GLB) == (SYSCFG_ITLINE18_SR_LPTIM2_GLB)) ? 1UL : 0UL);
1208	}
1209	#endif /* SYSCFG_ITLINE18_SR_LPTIM2_GLB */
1210
1211	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
1212	/**
1213	* @brief Check if Timer 14 interrupt occurred or not.
1214	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
1215	* @retval State of bit (1 or 0).
1216	*/
1217	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
1218	{
1219	return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL);
1220	}
1221	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
1222
1223	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
1224	/**
1225	* @brief Check if Timer 15 interrupt occurred or not.
1226	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
1227	* @retval State of bit (1 or 0).
1228	*/
1229	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
1230	{
1231	return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)) ? 1UL : 0UL);
1232	}
1233	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
1234
1235	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
1236	/**
1237	* @brief Check if Timer 16 interrupt occurred or not.
1238	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
1239	* @retval State of bit (1 or 0).
1240	*/
1241	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
1242	{
1243	return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL);
1244	}
1245	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
1246
1247	#if defined(SYSCFG_ITLINE21_SR_FDCAN1_IT0)
1248	/**
1249	* @brief Check if FDCAN1_IT0 interrupt occurred or not.
1250	* @rmtoll SYSCFG_ITLINE21 SR_FDCAN1_IT0 LL_SYSCFG_IsActiveFlag_FDCAN1_IT0
1251	* @retval State of bit (1 or 0).
1252	*/
1253	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0(void)
1254	{
1255	return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN1_IT0) == (SYSCFG_ITLINE21_SR_FDCAN1_IT0)) ? 1UL : 0UL);
1256	}
1257	#endif /* SYSCFG_ITLINE21_SR_FDCAN1_IT0 */
1258	#if defined(SYSCFG_ITLINE21_SR_FDCAN2_IT0)
1259	/**
1260	* @brief Check if FDCAN2_IT0 interrupt occurred or not.
1261	* @rmtoll SYSCFG_ITLINE21 SR_FDCAN2_IT0 LL_SYSCFG_IsActiveFlag_FDCAN2_IT0
1262	* @retval State of bit (1 or 0).
1263	*/
1264	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT0(void)
1265	{
1266	return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN2_IT0) == (SYSCFG_ITLINE21_SR_FDCAN2_IT0)) ? 1UL : 0UL);
1267	}
1268	#endif /* SYSCFG_ITLINE21_SR_FDCAN2_IT0 */
1269
1270	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
1271	/**
1272	* @brief Check if Timer 17 interrupt occurred or not.
1273	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
1274	* @retval State of bit (1 or 0).
1275	*/
1276	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
1277	{
1278	return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL);
1279	}
1280	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
1281
1282	#if defined(SYSCFG_ITLINE22_SR_FDCAN1_IT1)
1283	/**
1284	* @brief Check if FDCAN1_IT1 interrupt occurred or not.
1285	* @rmtoll SYSCFG_ITLINE22 SR_FDCAN1_IT1 LL_SYSCFG_IsActiveFlag_FDCAN1_IT1
1286	* @retval State of bit (1 or 0).
1287	*/
1288	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1(void)
1289	{
1290	return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN1_IT1) == (SYSCFG_ITLINE22_SR_FDCAN1_IT1)) ? 1UL : 0UL);
1291	}
1292	#endif /* SYSCFG_ITLINE22_SR_FDCAN1_IT1 */
1293	#if defined(SYSCFG_ITLINE22_SR_FDCAN2_IT1)
1294	/**
1295	* @brief Check if FDCAN2_IT1 interrupt occurred or not.
1296	* @rmtoll SYSCFG_ITLINE22 SR_FDCAN2_IT1 LL_SYSCFG_IsActiveFlag_FDCAN2_IT1
1297	* @retval State of bit (1 or 0).
1298	*/
1299	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT1(void)
1300	{
1301	return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN2_IT1) == (SYSCFG_ITLINE22_SR_FDCAN2_IT1)) ? 1UL : 0UL);
1302	}
1303	#endif /* SYSCFG_ITLINE22_SR_FDCAN2_IT1 */
1304
1305	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
1306	/**
1307	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
1308	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
1309	* @retval State of bit (1 or 0).
1310	*/
1311	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
1312	{
1313	return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL);
1314	}
1315	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
1316
1317	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
1318	/**
1319	* @brief Check if I2C2 interrupt occurred or not.
1320	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
1321	* @retval State of bit (1 or 0).
1322	*/
1323	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
1324	{
1325	return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)) ? 1UL : 0UL);
1326	}
1327	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
1328
1329	#if defined(SYSCFG_ITLINE24_SR_I2C3_GLB)
1330	/**
1331	* @brief Check if I2C3 interrupt occurred or not.
1332	* @rmtoll SYSCFG_ITLINE24 SR_I2C3_GLB LL_SYSCFG_IsActiveFlag_I2C3
1333	* @retval State of bit (1 or 0).
1334	*/
1335	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C3(void)
1336	{
1337	return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C3_GLB) == (SYSCFG_ITLINE24_SR_I2C3_GLB)) ? 1UL : 0UL);
1338	}
1339	#endif /* SYSCFG_ITLINE24_SR_I2C3_GLB */
1340
1341	#if defined(SYSCFG_ITLINE25_SR_SPI1)
1342	/**
1343	* @brief Check if SPI1 interrupt occurred or not.
1344	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
1345	* @retval State of bit (1 or 0).
1346	*/
1347	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
1348	{
1349	return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
1350	}
1351	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
1352
1353	#if defined(SYSCFG_ITLINE26_SR_SPI2)
1354	/**
1355	* @brief Check if SPI2 interrupt occurred or not.
1356	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
1357	* @retval State of bit (1 or 0).
1358	*/
1359	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
1360	{
1361	return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL);
1362	}
1363	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
1364
1365	#if defined(SYSCFG_ITLINE26_SR_SPI3)
1366	/**
1367	* @brief Check if SPI3 interrupt occurred or not.
1368	* @rmtoll SYSCFG_ITLINE26 SR_SPI3 LL_SYSCFG_IsActiveFlag_SPI3
1369	* @retval State of bit (1 or 0).
1370	*/
1371	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI3(void)
1372	{
1373	return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI3) == (SYSCFG_ITLINE26_SR_SPI3)) ? 1UL : 0UL);
1374	}
1375	#endif /* SYSCFG_ITLINE26_SR_SPI3 */
1376
1377	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
1378	/**
1379	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
1380	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
1381	* @retval State of bit (1 or 0).
1382	*/
1383	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
1384	{
1385	return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL);
1386	}
1387	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
1388
1389	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
1390	/**
1391	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
1392	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
1393	* @retval State of bit (1 or 0).
1394	*/
1395	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
1396	{
1397	return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL);
1398	}
1399	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
1400
1401	#if defined(SYSCFG_ITLINE28_SR_LPUART2_GLB)
1402	/**
1403	* @brief Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.
1404	* @rmtoll SYSCFG_ITLINE28 SR_LPUART2_GLB LL_SYSCFG_IsActiveFlag_LPUART2
1405	* @retval State of bit (1 or 0).
1406	*/
1407	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART2(void)
1408	{
1409	return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_LPUART2_GLB) == (SYSCFG_ITLINE28_SR_LPUART2_GLB)) ? 1UL : 0UL);
1410	}
1411	#endif /* SYSCFG_ITLINE28_SR_LPUART2_GLB */
1412
1413	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
1414	/**
1415	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
1416	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
1417	* @retval State of bit (1 or 0).
1418	*/
1419	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
1420	{
1421	return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)) ? 1UL : 0UL);
1422	}
1423	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
1424
1425	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
1426	/**
1427	* @brief Check if USART4 interrupt occurred or not.
1428	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
1429	* @retval State of bit (1 or 0).
1430	*/
1431	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
1432	{
1433	return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)) ? 1UL : 0UL);
1434	}
1435	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
1436
1437	#if defined(SYSCFG_ITLINE29_SR_LPUART1_GLB)
1438	/**
1439	* @brief Check if LPUART1 interrupt occurred or not.
1440	* @rmtoll SYSCFG_ITLINE29 SR_LPUART1_GLB LL_SYSCFG_IsActiveFlag_LPUART1
1441	* @retval State of bit (1 or 0).
1442	*/
1443	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART1(void)
1444	{
1445	return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_LPUART1_GLB) == (SYSCFG_ITLINE29_SR_LPUART1_GLB)) ? 1UL : 0UL);
1446	}
1447	#endif /* SYSCFG_ITLINE29_SR_LPUART1_GLB */
1448
1449	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
1450	/**
1451	* @brief Check if USART5 interrupt occurred or not.
1452	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
1453	* @retval State of bit (1 or 0).
1454	*/
1455	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
1456	{
1457	return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)) ? 1UL : 0UL);
1458	}
1459	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
1460
1461	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
1462	/**
1463	* @brief Check if USART6 interrupt occurred or not.
1464	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
1465	* @retval State of bit (1 or 0).
1466	*/
1467	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
1468	{
1469	return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)) ? 1UL : 0UL);
1470	}
1471	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
1472
1473	#if defined(SYSCFG_ITLINE30_SR_CEC)
1474	/**
1475	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
1476	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
1477	* @retval State of bit (1 or 0).
1478	*/
1479	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
1480	{
1481	return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)) ? 1UL : 0UL);
1482	}
1483	#endif /* SYSCFG_ITLINE30_SR_CEC */
1484
1485	#if defined(SYSCFG_ITLINE31_SR_AES)
1486	/**
1487	* @brief Check if AES interrupt occurred or not
1488	* @rmtoll SYSCFG_ITLINE31 SR_AES LL_SYSCFG_IsActiveFlag_AES
1489	* @retval State of bit (1 or 0).
1490	*/
1491	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_AES(void)
1492	{
1493	return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_AES) == (SYSCFG_ITLINE31_SR_AES)) ? 1UL : 0UL);
1494	}
1495	#endif /* SYSCFG_ITLINE31_SR_AES */
1496
1497	#if defined(SYSCFG_ITLINE31_SR_RNG)
1498	/**
1499	* @brief Check if RNG interrupt occurred or not, combined with EXTI line 31.
1500	* @rmtoll SYSCFG_ITLINE31 SR_RNG LL_SYSCFG_IsActiveFlag_RNG
1501	* @retval State of bit (1 or 0).
1502	*/
1503	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RNG(void)
1504	{
1505	return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_RNG) == (SYSCFG_ITLINE31_SR_RNG)) ? 1UL : 0UL);
1506	}
1507	#endif /* SYSCFG_ITLINE31_SR_RNG */
1508
1509	/**
1510	* @brief Set connections to TIM1/15/16/17 Break inputs
1511	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
1512	* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
1513	* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
1514	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
1515	* @param Break This parameter can be a combination of the following values:
1516	* @ifnot STM32G070xx
1517	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1518	* @endif
1519	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
1520	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1521	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
1522	*
1523	* (*) value not defined in all devices
1524	* @retval None
1525	*/
1526	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1527	{
1528	#if defined(SYSCFG_CFGR2_PVDL)
1529	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL, Break);
1530	#else
1531	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_ECCL, Break);
1532	#endif /SYSCFG_CFGR2_PVDL/
1533	}
1534
1535	/**
1536	* @brief Get connections to TIM1/15/16/17 Break inputs
1537	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
1538	* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
1539	* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
1540	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
1541	* @retval Returned value can be can be a combination of the following values:
1542	* @ifnot STM32G070xx
1543	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1544	* @endif
1545	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
1546	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1547	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
1548	*
1549	* (*) value not defined in all devices
1550	*/
1551	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1552	{
1553	#if defined(SYSCFG_CFGR2_PVDL)
1554	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL));
1555	#else
1556	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_ECCL));
1557	#endif /SYSCFG_CFGR2_PVDL/
1558	}
1559
1560	/**
1561	* @brief Check if SRAM parity error detected
1562	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
1563	* @retval State of bit (1 or 0).
1564	*/
1565	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1566	{
1567	return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
1568	}
1569
1570	/**
1571	* @brief Clear SRAM parity error flag
1572	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
1573	* @retval None
1574	*/
1575	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1576	{
1577	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
1578	}
1579
1580	#if defined(SYSCFG_CDEN_SUPPORT)
1581	/**
1582	* @brief Enable Clamping Diode on specific pin
1583	* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_EnableClampingDiode\n
1584	* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_EnableClampingDiode\n
1585	* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_EnableClampingDiode\n
1586	* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_EnableClampingDiode\n
1587	* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_EnableClampingDiode\n
1588	* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_EnableClampingDiode\n
1589	* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_EnableClampingDiode\n
1590	* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_EnableClampingDiode
1591	* @param ConfigClampingDiode This parameter can be a combination of the following values:
1592	* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
1593	* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
1594	* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
1595	* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
1596	* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
1597	* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
1598	* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
1599	* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
1600	* @retval None
1601	*/
1602	__STATIC_INLINE void LL_SYSCFG_EnableClampingDiode(uint32_t ConfigClampingDiode)
1603	{
1604	SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
1605	}
1606
1607	/**
1608	* @brief Disable Clamping Diode on specific pin
1609	* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_DisableClampingDiode\n
1610	* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_DisableClampingDiode\n
1611	* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_DisableClampingDiode\n
1612	* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_DisableClampingDiode\n
1613	* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_DisableClampingDiode\n
1614	* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_DisableClampingDiode\n
1615	* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_DisableClampingDiode\n
1616	* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_DisableClampingDiode
1617	* @param ConfigClampingDiode This parameter can be a combination of the following values:
1618	* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
1619	* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
1620	* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
1621	* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
1622	* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
1623	* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
1624	* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
1625	* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
1626	* @retval None
1627	*/
1628	__STATIC_INLINE void LL_SYSCFG_DisableClampingDiode(uint32_t ConfigClampingDiode)
1629	{
1630	CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
1631	}
1632	/**
1633	* @brief Indicates whether clamping diode(s) is(are) enabled.
1634	* @rmtoll SYSCFG_CFGR2 PA1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1635	* SYSCFG_CFGR2 PA3_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1636	* SYSCFG_CFGR2 PA5_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1637	* SYSCFG_CFGR2 PA6_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1638	* SYSCFG_CFGR2 PA13_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1639	* SYSCFG_CFGR2 PB0_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1640	* SYSCFG_CFGR2 PB1_CDEN LL_SYSCFG_IsEnabledClampingDiode\n
1641	* SYSCFG_CFGR1 PB2_CDEN LL_SYSCFG_IsEnabledClampingDiode
1642	* @param ConfigClampingDiode This parameter can be a combination of the following values:
1643	* @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
1644	* @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
1645	* @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
1646	* @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
1647	* @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
1648	* @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
1649	* @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
1650	* @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
1651	* @retval None
1652	*/
1653	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode(uint32_t ConfigClampingDiode)
1654	{
1655	return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL);
1656	}
1657	#endif /* SYSCFG_CDEN_SUPPORT */
1658
1659	/**
1660	* @}
1661	*/
1662
1663	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1664	* @{
1665	*/
1666
1667	/**
1668	* @brief Return the device identifier
1669	* @note For STM32G081xx devices, the device ID is 0x460
1670	* @rmtoll DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1671	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1672	*/
1673	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1674	{
1675	return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID));
1676	}
1677
1678	/**
1679	* @brief Return the device revision identifier
1680	* @note This field indicates the revision of the device.
1681	* @rmtoll DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1682	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1683	*/
1684	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1685	{
1686	return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos);
1687	}
1688
1689	/**
1690	* @brief Enable the Debug Module during STOP mode
1691	* @rmtoll DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1692	* @retval None
1693	*/
1694	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1695	{
1696	SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
1697	}
1698
1699	/**
1700	* @brief Disable the Debug Module during STOP mode
1701	* @rmtoll DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1702	* @retval None
1703	*/
1704	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1705	{
1706	CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
1707	}
1708
1709	/**
1710	* @brief Enable the Debug Module during STANDBY mode
1711	* @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1712	* @retval None
1713	*/
1714	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1715	{
1716	SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
1717	}
1718
1719	/**
1720	* @brief Disable the Debug Module during STANDBY mode
1721	* @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1722	* @retval None
1723	*/
1724	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1725	{
1726	CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
1727	}
1728
1729	/**
1730	* @brief Freeze APB1 peripherals (group1 peripherals)
1731	* @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1732	* DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1733	* DBG_APB_FZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1734	* DBG_APB_FZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1735	* DBG_APB_FZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1736	* DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1737	* DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1738	* DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1739	* DBG_APB_FZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1740	* DBG_APB_FZ1 DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1741	* DBG_APB_FZ1 DBG_LPTIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1742	* DBG_APB_FZ1 DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1743	* @param Periphs This parameter can be a combination of the following values:
1744	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1745	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1746	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1747	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1748	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1749	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1750	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1751	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1752	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1753	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1754	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
1755	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
1756	*
1757	* (*) value not defined in all devices
1758	* @retval None
1759	*/
1760	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1761	{
1762	SET_BIT(DBG->APBFZ1, Periphs);
1763	}
1764
1765	/**
1766	* @brief Unfreeze APB1 peripherals (group1 peripherals)
1767	* @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1768	* DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1769	* DBG_APB_FZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1770	* DBG_APB_FZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1771	* DBG_APB_FZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1772	* DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1773	* DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1774	* DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1775	* DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1776	* DBG_APB_FZ1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1777	* DBG_APB_FZ1 DBG_LPTIM2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1778	* DBG_APB_FZ1 DBG_LPTIM1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1779	* @param Periphs This parameter can be a combination of the following values:
1780	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1781	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1782	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1783	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1784	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1785	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1786	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1787	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1788	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1789	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1790	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
1791	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
1792	*
1793	* (*) value not defined in all devices
1794	* @retval None
1795	*/
1796	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1797	{
1798	CLEAR_BIT(DBG->APBFZ1, Periphs);
1799	}
1800
1801	/**
1802	* @brief Freeze APB2 peripherals
1803	* @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1804	* DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1805	* DBG_APB_FZ2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1806	* DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1807	* DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1808	* @param Periphs This parameter can be a combination of the following values:
1809	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1810	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
1811	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
1812	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1813	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1814	*
1815	* (*) value not defined in all devices
1816	* @retval None
1817	*/
1818	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1819	{
1820	SET_BIT(DBG->APBFZ2, Periphs);
1821	}
1822
1823	/**
1824	* @brief Unfreeze APB2 peripherals
1825	* @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1826	* DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1827	* DBG_APB_FZ2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1828	* DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1829	* DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1830	* @param Periphs This parameter can be a combination of the following values:
1831	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1832	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
1833	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
1834	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1835	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1836	*
1837	* (*) value not defined in all devices
1838	* @retval None
1839	*/
1840	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1841	{
1842	CLEAR_BIT(DBG->APBFZ2, Periphs);
1843	}
1844	/**
1845	* @}
1846	*/
1847
1848	#if defined(VREFBUF)
1849	/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1850	* @{
1851	*/
1852
1853	/**
1854	* @brief Enable Internal voltage reference
1855	* @rmtoll VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Enable
1856	* @retval None
1857	*/
1858	__STATIC_INLINE void LL_VREFBUF_Enable(void)
1859	{
1860	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1861	}
1862
1863	/**
1864	* @brief Disable Internal voltage reference
1865	* @rmtoll VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Disable
1866	* @retval None
1867	*/
1868	__STATIC_INLINE void LL_VREFBUF_Disable(void)
1869	{
1870	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1871	}
1872
1873	/**
1874	* @brief Enable high impedance (VREF+pin is high impedance)
1875	* @rmtoll VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_EnableHIZ
1876	* @retval None
1877	*/
1878	__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1879	{
1880	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1881	}
1882
1883	/**
1884	* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1885	* @rmtoll VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_DisableHIZ
1886	* @retval None
1887	*/
1888	__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1889	{
1890	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1891	}
1892
1893	/**
1894	* @brief Set the Voltage reference scale
1895	* @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_SetVoltageScaling
1896	* @param Scale This parameter can be one of the following values:
1897	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1898	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1899	* @retval None
1900	*/
1901	__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1902	{
1903	MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1904	}
1905
1906	/**
1907	* @brief Get the Voltage reference scale
1908	* @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_GetVoltageScaling
1909	* @retval Returned value can be one of the following values:
1910	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1911	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1912	*/
1913	__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1914	{
1915	return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1916	}
1917
1918	/**
1919	* @brief Check if Voltage reference buffer is ready
1920	* @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_IsVREFReady
1921	* @retval State of bit (1 or 0).
1922	*/
1923	__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1924	{
1925	return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1926	}
1927
1928	/**
1929	* @brief Get the trimming code for VREFBUF calibration
1930	* @rmtoll VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_GetTrimming
1931	* @retval Between 0 and 0x3F
1932	*/
1933	__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1934	{
1935	return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1936	}
1937
1938	/**
1939	* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1940	* @note VrefBuf voltage scale is calibrated in production for each device,
1941	* using voltage scale 1. This calibration value is loaded
1942	* as default trimming value at device power up.
1943	* This trimming value can be fine tuned for voltage scales 0 and 1
1944	* using this function.
1945	* @rmtoll VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_SetTrimming
1946	* @param Value Between 0 and 0x3F
1947	* @retval None
1948	*/
1949	__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1950	{
1951	WRITE_REG(VREFBUF->CCR, Value);
1952	}
1953
1954	/**
1955	* @}
1956	*/
1957	#endif /* VREFBUF */
1958
1959	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
1960	* @{
1961	*/
1962
1963	/**
1964	* @brief Set FLASH Latency
1965	* @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency
1966	* @param Latency This parameter can be one of the following values:
1967	* @arg @ref LL_FLASH_LATENCY_0
1968	* @arg @ref LL_FLASH_LATENCY_1
1969	* @arg @ref LL_FLASH_LATENCY_2
1970	* @retval None
1971	*/
1972	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1973	{
1974	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1975	}
1976
1977	/**
1978	* @brief Get FLASH Latency
1979	* @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency
1980	* @retval Returned value can be one of the following values:
1981	* @arg @ref LL_FLASH_LATENCY_0
1982	* @arg @ref LL_FLASH_LATENCY_1
1983	* @arg @ref LL_FLASH_LATENCY_2
1984	*/
1985	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1986	{
1987	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1988	}
1989
1990	/**
1991	* @brief Enable Prefetch
1992	* @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch
1993	* @retval None
1994	*/
1995	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1996	{
1997	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1998	}
1999
2000	/**
2001	* @brief Disable Prefetch
2002	* @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch
2003	* @retval None
2004	*/
2005	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
2006	{
2007	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
2008	}
2009
2010	/**
2011	* @brief Check if Prefetch buffer is enabled
2012	* @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled
2013	* @retval State of bit (1 or 0).
2014	*/
2015	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
2016	{
2017	return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
2018	}
2019
2020	/**
2021	* @brief Enable Instruction cache
2022	* @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache
2023	* @retval None
2024	*/
2025	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
2026	{
2027	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
2028	}
2029
2030	/**
2031	* @brief Disable Instruction cache
2032	* @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache
2033	* @retval None
2034	*/
2035	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
2036	{
2037	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
2038	}
2039
2040	/**
2041	* @brief Enable Instruction cache reset
2042	* @note bit can be written only when the instruction cache is disabled
2043	* @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset
2044	* @retval None
2045	*/
2046	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
2047	{
2048	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2049	}
2050
2051	/**
2052	* @brief Disable Instruction cache reset
2053	* @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset
2054	* @retval None
2055	*/
2056	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
2057	{
2058	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2059	}
2060
2061	/**
2062	* @}
2063	*/
2064
2065	/**
2066	* @}
2067	*/
2068
2069	/**
2070	* @}
2071	*/
2072
2073	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBG) */
2074
2075	/**
2076	* @}
2077	*/
2078
2079	#ifdef __cplusplus
2080	}
2081	#endif
2082
2083	#endif /* STM32G0xx_LL_SYSTEM_H */
2084
2085

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h

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