Context Navigation

stm32g0xx_ll_dma.c

Last change on this file was 6, checked in by f.jahn, 3 months ago

File size: 14.3 KB

Line
1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_dma.c
4	* @author MCD Application Team
5	* @brief DMA LL module driver.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19	#if defined(USE_FULL_LL_DRIVER)
20
21	/* Includes ------------------------------------------------------------------*/
22	#include "stm32g0xx_ll_dma.h"
23	#include "stm32g0xx_ll_bus.h"
24	#ifdef USE_FULL_ASSERT
25	#include "stm32_assert.h"
26	#else
27	#define assert_param(expr) ((void)0U)
28	#endif
29
30	/** @addtogroup STM32G0xx_LL_Driver
31	* @{
32	*/
33
34	#if defined (DMA1)
35
36	/** @defgroup DMA_LL DMA
37	* @{
38	*/
39
40	/* Private types -------------------------------------------------------------*/
41	/* Private variables ---------------------------------------------------------*/
42	/* Private constants ---------------------------------------------------------*/
43	/* Private macros ------------------------------------------------------------*/
44	/** @addtogroup DMA_LL_Private_Macros
45	* @{
46	*/
47	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
48	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
49	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
50
51	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
52	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
53
54	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
55	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
56
57	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
58	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
59
60	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
61	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
62	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
63
64	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
65	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
66	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
67
68	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
69
70	#if defined(STM32G081xx)\|\|defined(STM32G071xx)
71	#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_UCPD2_TX)
72	#elif defined(STM32G070xx)
73	#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_USART4_TX)
74	#elif defined(STM32G041xx)\|\|defined(STM32G031xx)\|\|defined(STM32G030xx)
75	#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_REQ_USART2_TX)
76	#endif
77
78	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
79	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
80	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
81	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
82
83	#if defined(STM32G081xx) \|\| defined(STM32G071xx) \|\| defined(STM32G070xx)
84	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
85	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
86	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
87	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
88	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
89	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
90	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
91	((CHANNEL) == LL_DMA_CHANNEL_7))))
92	#elif defined(STM32G041xx) \|\| defined(STM32G031xx) \|\| defined(STM32G030xx)
93	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
94	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
95	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
96	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
97	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
98	((CHANNEL) == LL_DMA_CHANNEL_5))))
99	#endif
100	/**
101	* @}
102	*/
103
104	/* Private function prototypes -----------------------------------------------*/
105
106	/* Exported functions --------------------------------------------------------*/
107	/** @addtogroup DMA_LL_Exported_Functions
108	* @{
109	*/
110
111	/** @addtogroup DMA_LL_EF_Init
112	* @{
113	*/
114
115	/**
116	* @brief De-initialize the DMA registers to their default reset values.
117	* @param DMAx DMAx Instance
118	* @param Channel This parameter can be one of the following values:
119	* @arg @ref LL_DMA_CHANNEL_1
120	* @arg @ref LL_DMA_CHANNEL_2
121	* @arg @ref LL_DMA_CHANNEL_3
122	* @arg @ref LL_DMA_CHANNEL_4
123	* @arg @ref LL_DMA_CHANNEL_5
124	* @arg @ref LL_DMA_CHANNEL_6
125	* @arg @ref LL_DMA_CHANNEL_7
126	* @arg @ref LL_DMA_CHANNEL_ALL
127	* @retval An ErrorStatus enumeration value:
128	* - SUCCESS: DMA registers are de-initialized
129	* - ERROR: DMA registers are not de-initialized
130	*/
131	ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
132	{
133	ErrorStatus status = SUCCESS;
134
135	/* Check the DMA Instance DMAx and Channel parameters*/
136	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) \|\| (Channel == LL_DMA_CHANNEL_ALL));
137
138	if (Channel == LL_DMA_CHANNEL_ALL)
139	{
140	if (DMAx == DMA1)
141	{
142	/* Force reset of DMA clock */
143	LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
144
145	/* Release reset of DMA clock */
146	LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
147	}
148	#if defined(DMA2)
149	else if (DMAx == DMA2)
150	{
151	/* Force reset of DMA clock */
152	LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
153
154	/* Release reset of DMA clock */
155	LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
156	}
157	#endif
158	else
159	{
160	status = ERROR;
161	}
162	}
163	else
164	{
165	DMA_Channel_TypeDef *tmp;
166
167	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
168
169	/* Disable the selected DMAx_Channely */
170	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
171
172	/* Reset DMAx_Channely control register */
173	WRITE_REG(tmp->CCR, 0U);
174
175	/* Reset DMAx_Channely remaining bytes register */
176	WRITE_REG(tmp->CNDTR, 0U);
177
178	/* Reset DMAx_Channely peripheral address register */
179	WRITE_REG(tmp->CPAR, 0U);
180
181	/* Reset DMAx_Channely memory address register */
182	WRITE_REG(tmp->CMAR, 0U);
183
184	/* Reset Request register field for DMAx Channel */
185	LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
186
187	if (Channel == LL_DMA_CHANNEL_1)
188	{
189	/* Reset interrupt pending bits for DMAx Channel1 */
190	LL_DMA_ClearFlag_GI1(DMAx);
191	}
192	else if (Channel == LL_DMA_CHANNEL_2)
193	{
194	/* Reset interrupt pending bits for DMAx Channel2 */
195	LL_DMA_ClearFlag_GI2(DMAx);
196	}
197	else if (Channel == LL_DMA_CHANNEL_3)
198	{
199	/* Reset interrupt pending bits for DMAx Channel3 */
200	LL_DMA_ClearFlag_GI3(DMAx);
201	}
202	else if (Channel == LL_DMA_CHANNEL_4)
203	{
204	/* Reset interrupt pending bits for DMAx Channel4 */
205	LL_DMA_ClearFlag_GI4(DMAx);
206	}
207	else if (Channel == LL_DMA_CHANNEL_5)
208	{
209	/* Reset interrupt pending bits for DMAx Channel5 */
210	LL_DMA_ClearFlag_GI5(DMAx);
211	}
212	#if defined(LL_DMA_CHANNEL_6)
213	else if (Channel == LL_DMA_CHANNEL_6)
214	{
215	/* Reset interrupt pending bits for DMAx Channel6 */
216	LL_DMA_ClearFlag_GI6(DMAx);
217	}
218	#endif /* LL_DMA_CHANNEL_6 */
219	#if defined(LL_DMA_CHANNEL_7)
220	else if (Channel == LL_DMA_CHANNEL_7)
221	{
222	/* Reset interrupt pending bits for DMAx Channel7 */
223	LL_DMA_ClearFlag_GI7(DMAx);
224	}
225	#endif /* LL_DMA_CHANNEL_7 */
226	else
227	{
228	status = ERROR;
229	}
230	}
231
232	return status;
233	}
234
235	/**
236	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
237	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
238	* @arg @ref __LL_DMA_GET_INSTANCE
239	* @arg @ref __LL_DMA_GET_CHANNEL
240	* @param DMAx DMAx Instance
241	* @param Channel This parameter can be one of the following values:
242	* @arg @ref LL_DMA_CHANNEL_1
243	* @arg @ref LL_DMA_CHANNEL_2
244	* @arg @ref LL_DMA_CHANNEL_3
245	* @arg @ref LL_DMA_CHANNEL_4
246	* @arg @ref LL_DMA_CHANNEL_5
247	* @arg @ref LL_DMA_CHANNEL_6
248	* @arg @ref LL_DMA_CHANNEL_7
249	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
250	* @retval An ErrorStatus enumeration value:
251	* - SUCCESS: DMA registers are initialized
252	* - ERROR: Not applicable
253	*/
254	ErrorStatus LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
255	{
256	/* Check the DMA Instance DMAx and Channel parameters*/
257	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
258
259	/* Check the DMA parameters from DMA_InitStruct */
260	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
261	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
262	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
263	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
264	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
265	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
266	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
267	assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
268	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
269
270	/*---------------------------- DMAx CCR Configuration ------------------------
271	* Configure DMAx_Channely: data transfer direction, data transfer mode,
272	* peripheral and memory increment mode,
273	* data size alignment and priority level with parameters :
274	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
275	* - Mode: DMA_CCR_CIRC bit
276	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
277	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
278	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
279	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
280	* - Priority: DMA_CCR_PL[1:0] bits
281	*/
282	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
283	DMA_InitStruct->Mode \| \
284	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
285	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
286	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
287	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
288	DMA_InitStruct->Priority);
289
290	/*-------------------------- DMAx CMAR Configuration -------------------------
291	* Configure the memory or destination base address with parameter :
292	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
293	*/
294	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
295
296	/*-------------------------- DMAx CPAR Configuration -------------------------
297	* Configure the peripheral or source base address with parameter :
298	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
299	*/
300	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
301
302	/*--------------------------- DMAx CNDTR Configuration -----------------------
303	* Configure the peripheral base address with parameter :
304	* - NbData: DMA_CNDTR_NDT[15:0] bits
305	*/
306	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
307
308	/*--------------------------- DMAMUXx CCR Configuration ----------------------
309	* Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
310	* - PeriphRequest: DMA_CxCR[7:0] bits
311	*/
312	LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
313
314	return SUCCESS;
315	}
316
317	/**
318	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
319	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
320	* @retval None
321	*/
322	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
323	{
324	/* Set DMA_InitStruct fields to default values */
325	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
326	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
327	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
328	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
329	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
330	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
331	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
332	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
333	DMA_InitStruct->NbData = 0x00000000U;
334	DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
335	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
336	}
337
338	/**
339	* @}
340	*/
341
342	/**
343	* @}
344	*/
345
346	/**
347	* @}
348	*/
349
350	#endif /* DMA1 */
351
352	/**
353	* @}
354	*/
355
356	#endif /* USE_FULL_LL_DRIVER */
357
358	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c

Download in other formats: