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stm32g0xx_ll_spi.c

Last change on this file was 6, checked in by f.jahn, 3 months ago

File size: 20.6 KB

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1	/**
2	******************************************************************************
3	* @file stm32g0xx_ll_spi.c
4	* @author MCD Application Team
5	* @brief SPI LL module driver.
6	******************************************************************************
7	* @attention
8	*
9	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
10	* All rights reserved.</center></h2>
11	*
12	* This software component is licensed by ST under BSD 3-Clause license,
13	* the "License"; You may not use this file except in compliance with the
14	* License. You may obtain a copy of the License at:
15	* opensource.org/licenses/BSD-3-Clause
16	*
17	******************************************************************************
18	*/
19	#if defined(USE_FULL_LL_DRIVER)
20
21	/* Includes ------------------------------------------------------------------*/
22	#include "stm32g0xx_ll_spi.h"
23	#include "stm32g0xx_ll_bus.h"
24	#include "stm32g0xx_ll_rcc.h"
25
26	#ifdef USE_FULL_ASSERT
27	#include "stm32_assert.h"
28	#else
29	#define assert_param(expr) ((void)0U)
30	#endif
31
32	/** @addtogroup STM32G0xx_LL_Driver
33	* @{
34	*/
35
36	#if defined (SPI1) \|\| defined (SPI2)
37
38	/** @addtogroup SPI_LL
39	* @{
40	*/
41
42	/* Private types -------------------------------------------------------------*/
43	/* Private variables ---------------------------------------------------------*/
44
45	/* Private constants ---------------------------------------------------------*/
46	/** @defgroup SPI_LL_Private_Constants SPI Private Constants
47	* @{
48	*/
49	/* SPI registers Masks */
50	#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA \| SPI_CR1_CPOL \| SPI_CR1_MSTR \| \
51	SPI_CR1_BR \| SPI_CR1_LSBFIRST \| SPI_CR1_SSI \| \
52	SPI_CR1_SSM \| SPI_CR1_RXONLY \| SPI_CR1_CRCL \| \
53	SPI_CR1_CRCNEXT \| SPI_CR1_CRCEN \| SPI_CR1_BIDIOE \| \
54	SPI_CR1_BIDIMODE)
55	/**
56	* @}
57	*/
58
59	/* Private macros ------------------------------------------------------------*/
60	/** @defgroup SPI_LL_Private_Macros SPI Private Macros
61	* @{
62	*/
63	#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
64	\|\| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
65	\|\| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
66	\|\| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
67
68	#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
69	\|\| ((__VALUE__) == LL_SPI_MODE_SLAVE))
70
71	#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
72	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
73	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
74	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
75	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
76	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
77	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
78	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
79	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
80	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
81	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
82	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
83	\|\| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
84
85	#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
86	\|\| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
87
88	#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
89	\|\| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
90
91	#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
92	\|\| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
93	\|\| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
94
95	#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
96	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
97	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
98	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
99	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
100	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
101	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
102	\|\| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
103
104	#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
105	\|\| ((__VALUE__) == LL_SPI_MSB_FIRST))
106
107	#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
108	\|\| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
109
110	#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
111
112	/**
113	* @}
114	*/
115
116	/* Private function prototypes -----------------------------------------------*/
117
118	/* Exported functions --------------------------------------------------------*/
119	/** @addtogroup SPI_LL_Exported_Functions
120	* @{
121	*/
122
123	/** @addtogroup SPI_LL_EF_Init
124	* @{
125	*/
126
127	/**
128	* @brief De-initialize the SPI registers to their default reset values.
129	* @param SPIx SPI Instance
130	* @retval An ErrorStatus enumeration value:
131	* - SUCCESS: SPI registers are de-initialized
132	* - ERROR: SPI registers are not de-initialized
133	*/
134	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
135	{
136	ErrorStatus status = ERROR;
137
138	/* Check the parameters */
139	assert_param(IS_SPI_ALL_INSTANCE(SPIx));
140
141	#if defined(SPI1)
142	if (SPIx == SPI1)
143	{
144	/* Force reset of SPI clock */
145	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
146
147	/* Release reset of SPI clock */
148	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
149
150	status = SUCCESS;
151	}
152	#endif /* SPI1 */
153	#if defined(SPI2)
154	if (SPIx == SPI2)
155	{
156	/* Force reset of SPI clock */
157	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
158
159	/* Release reset of SPI clock */
160	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
161
162	status = SUCCESS;
163	}
164	#endif /* SPI2 */
165
166	return status;
167	}
168
169	/**
170	* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
171	* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
172	* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
173	* @param SPIx SPI Instance
174	* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
175	* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
176	*/
177	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct)
178	{
179	ErrorStatus status = ERROR;
180
181	/* Check the SPI Instance SPIx*/
182	assert_param(IS_SPI_ALL_INSTANCE(SPIx));
183
184	/* Check the SPI parameters from SPI_InitStruct*/
185	assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
186	assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
187	assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
188	assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
189	assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
190	assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
191	assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
192	assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
193	assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
194
195	if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
196	{
197	/*---------------------------- SPIx CR1 Configuration ------------------------
198	* Configure SPIx CR1 with parameters:
199	* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
200	* - Master/Slave Mode: SPI_CR1_MSTR bit
201	* - ClockPolarity: SPI_CR1_CPOL bit
202	* - ClockPhase: SPI_CR1_CPHA bit
203	* - NSS management: SPI_CR1_SSM bit
204	* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
205	* - BitOrder: SPI_CR1_LSBFIRST bit
206	* - CRCCalculation: SPI_CR1_CRCEN bit
207	*/
208	MODIFY_REG(SPIx->CR1,
209	SPI_CR1_CLEAR_MASK,
210	SPI_InitStruct->TransferDirection \| SPI_InitStruct->Mode \|
211	SPI_InitStruct->ClockPolarity \| SPI_InitStruct->ClockPhase \|
212	SPI_InitStruct->NSS \| SPI_InitStruct->BaudRate \|
213	SPI_InitStruct->BitOrder \| SPI_InitStruct->CRCCalculation);
214
215	/*---------------------------- SPIx CR2 Configuration ------------------------
216	* Configure SPIx CR2 with parameters:
217	* - DataWidth: DS[3:0] bits
218	* - NSS management: SSOE bit
219	*/
220	MODIFY_REG(SPIx->CR2,
221	SPI_CR2_DS \| SPI_CR2_SSOE,
222	SPI_InitStruct->DataWidth \| (SPI_InitStruct->NSS >> 16U));
223
224	/*---------------------------- SPIx CRCPR Configuration ----------------------
225	* Configure SPIx CRCPR with parameters:
226	* - CRCPoly: CRCPOLY[15:0] bits
227	*/
228	if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
229	{
230	assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
231	LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
232	}
233	status = SUCCESS;
234	}
235
236	#if defined (SPI_I2S_SUPPORT)
237	/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
238	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
239	#endif /* SPI_I2S_SUPPORT */
240	return status;
241	}
242
243	/**
244	* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
245	* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
246	* whose fields will be set to default values.
247	* @retval None
248	*/
249	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
250	{
251	/* Set SPI_InitStruct fields to default values */
252	SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
253	SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
254	SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
255	SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
256	SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
257	SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
258	SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
259	SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
260	SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
261	SPI_InitStruct->CRCPoly = 7U;
262	}
263
264	/**
265	* @}
266	*/
267
268	/**
269	* @}
270	*/
271
272	/**
273	* @}
274	*/
275
276	#if defined(SPI_I2S_SUPPORT)
277	/** @addtogroup I2S_LL
278	* @{
279	*/
280
281	/* Private types -------------------------------------------------------------*/
282	/* Private variables ---------------------------------------------------------*/
283	/* Private constants ---------------------------------------------------------*/
284	/** @defgroup I2S_LL_Private_Constants I2S Private Constants
285	* @{
286	*/
287	/* I2S registers Masks */
288	#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \| \
289	SPI_I2SCFGR_CKPOL \| SPI_I2SCFGR_I2SSTD \| \
290	SPI_I2SCFGR_I2SCFG \| SPI_I2SCFGR_I2SMOD )
291
292	#define I2S_I2SPR_CLEAR_MASK 0x0002U
293	/**
294	* @}
295	*/
296	/* Private macros ------------------------------------------------------------*/
297	/** @defgroup I2S_LL_Private_Macros I2S Private Macros
298	* @{
299	*/
300
301	#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
302	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
303	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
304	\|\| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
305
306	#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
307	\|\| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
308
309	#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
310	\|\| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
311	\|\| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
312	\|\| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
313	\|\| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
314
315	#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
316	\|\| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
317	\|\| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
318	\|\| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
319
320	#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
321	\|\| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
322
323	#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
324	&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
325	\|\| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
326
327	#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
328
329	#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
330	\|\| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
331	/**
332	* @}
333	*/
334
335	/* Private function prototypes -----------------------------------------------*/
336
337	/* Exported functions --------------------------------------------------------*/
338	/** @addtogroup I2S_LL_Exported_Functions
339	* @{
340	*/
341
342	/** @addtogroup I2S_LL_EF_Init
343	* @{
344	*/
345
346	/**
347	* @brief De-initialize the SPI/I2S registers to their default reset values.
348	* @param SPIx SPI Instance
349	* @retval An ErrorStatus enumeration value:
350	* - SUCCESS: SPI registers are de-initialized
351	* - ERROR: SPI registers are not de-initialized
352	*/
353	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
354	{
355	return LL_SPI_DeInit(SPIx);
356	}
357
358	/**
359	* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
360	* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
361	* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
362	* @param SPIx SPI Instance
363	* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
364	* @retval An ErrorStatus enumeration value:
365	* - SUCCESS: SPI registers are Initialized
366	* - ERROR: SPI registers are not Initialized
367	*/
368	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct)
369	{
370	uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
371	uint32_t tmp;
372	LL_RCC_ClocksTypeDef rcc_clocks;
373	uint32_t sourceclock;
374	ErrorStatus status = ERROR;
375
376	/* Check the I2S parameters */
377	assert_param(IS_I2S_ALL_INSTANCE(SPIx));
378	assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
379	assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
380	assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
381	assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
382	assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
383	assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
384
385	if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
386	{
387	/*---------------------------- SPIx I2SCFGR Configuration --------------------
388	* Configure SPIx I2SCFGR with parameters:
389	* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
390	* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
391	* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
392	* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
393	*/
394
395	/* Write to SPIx I2SCFGR */
396	MODIFY_REG(SPIx->I2SCFGR,
397	I2S_I2SCFGR_CLEAR_MASK,
398	I2S_InitStruct->Mode \| I2S_InitStruct->Standard \|
399	I2S_InitStruct->DataFormat \| I2S_InitStruct->ClockPolarity \|
400	SPI_I2SCFGR_I2SMOD);
401
402	/*---------------------------- SPIx I2SPR Configuration ----------------------
403	* Configure SPIx I2SPR with parameters:
404	* - MCLKOutput: SPI_I2SPR_MCKOE bit
405	* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
406	*/
407
408	/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
409	* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
410	*/
411	if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
412	{
413	/* Check the frame length (For the Prescaler computing)
414	* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
415	*/
416	if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
417	{
418	/* Packet length is 32 bits */
419	packetlength = 2U;
420	}
421
422	/* I2S Clock source is System clock: Get System Clock frequency */
423	LL_RCC_GetSystemClocksFreq(&rcc_clocks);
424
425	/* Get the source clock value: based on System Clock value */
426	sourceclock = rcc_clocks.SYSCLK_Frequency;
427
428	/* Compute the Real divider depending on the MCLK output state with a floating point */
429	if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
430	{
431	/* MCLK output is enabled */
432	tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
433	}
434	else
435	{
436	/* MCLK output is disabled */
437	tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
438	}
439
440	/* Remove the floating point */
441	tmp = tmp / 10U;
442
443	/* Check the parity of the divider */
444	i2sodd = (tmp & (uint16_t)0x0001U);
445
446	/* Compute the i2sdiv prescaler */
447	i2sdiv = ((tmp - i2sodd) / 2U);
448
449	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
450	i2sodd = (i2sodd << 8U);
451	}
452
453	/* Test if the divider is 1 or 0 or greater than 0xFF */
454	if ((i2sdiv < 2U) \|\| (i2sdiv > 0xFFU))
455	{
456	/* Set the default values */
457	i2sdiv = 2U;
458	i2sodd = 0U;
459	}
460
461	/* Write to SPIx I2SPR register the computed value */
462	WRITE_REG(SPIx->I2SPR, i2sdiv \| i2sodd \| I2S_InitStruct->MCLKOutput);
463
464	status = SUCCESS;
465	}
466	return status;
467	}
468
469	/**
470	* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
471	* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
472	* whose fields will be set to default values.
473	* @retval None
474	*/
475	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
476	{
477	/--------------- Reset I2S init structure parameters values -----------------/
478	I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
479	I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
480	I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
481	I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
482	I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
483	I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
484	}
485
486	/**
487	* @brief Set linear and parity prescaler.
488	* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
489	* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
490	* @param SPIx SPI Instance
491	* @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
492	* @param PrescalerParity This parameter can be one of the following values:
493	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
494	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
495	* @retval None
496	*/
497	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
498	{
499	/* Check the I2S parameters */
500	assert_param(IS_I2S_ALL_INSTANCE(SPIx));
501	assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
502	assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
503
504	/* Write to SPIx I2SPR */
505	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV \| SPI_I2SPR_ODD, PrescalerLinear \| (PrescalerParity << 8U));
506	}
507
508	/**
509	* @}
510	*/
511
512	/**
513	* @}
514	*/
515
516	/**
517	* @}
518	*/
519	#endif /* SPI_I2S_SUPPORT */
520
521	#endif /* defined (SPI1) \|\| defined (SPI2) */
522
523	/**
524	* @}
525	*/
526
527	#endif /* USE_FULL_LL_DRIVER */
528
529	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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source: trunk/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c

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