| [6] | 1 | /********************************************************************* |
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| 2 | * SEGGER Microcontroller GmbH * |
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| 3 | * The Embedded Experts * |
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| 4 | ********************************************************************** |
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| 5 | * * |
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| 6 | * (c) 2014 - 2019 SEGGER Microcontroller GmbH * |
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| 7 | * * |
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| 8 | * www.segger.com Support: support@segger.com * |
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| 9 | * * |
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| 10 | ********************************************************************** |
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| 11 | * * |
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| 12 | * All rights reserved. * |
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| 13 | * * |
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| 14 | * Redistribution and use in source and binary forms, with or * |
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| 15 | * without modification, are permitted provided that the following * |
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| 16 | * conditions are met: * |
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| 17 | * * |
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| 18 | * - Redistributions of source code must retain the above copyright * |
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| 19 | * notice, this list of conditions and the following disclaimer. * |
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| 20 | * * |
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| 21 | * - Neither the name of SEGGER Microcontroller GmbH * |
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| 22 | * nor the names of its contributors may be used to endorse or * |
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| 23 | * promote products derived from this software without specific * |
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| 24 | * prior written permission. * |
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| 25 | * * |
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| 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * |
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| 27 | * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * |
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| 28 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * |
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| 29 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * |
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| 30 | * DISCLAIMED. * |
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| 31 | * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * |
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * |
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| 33 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * |
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| 34 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * |
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| 35 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * |
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| 36 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * |
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| 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * |
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| 38 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * |
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| 39 | * DAMAGE. * |
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| 40 | * * |
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| 41 | *********************************************************************/ |
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| 42 | |
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| 43 | /***************************************************************************** |
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| 44 | * Preprocessor Definitions * |
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| 45 | * ------------------------ * |
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| 46 | * NO_STACK_INIT * |
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| 47 | * * |
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| 48 | * If defined, the stack pointer will not be initialised. * |
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| 49 | * * |
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| 50 | * NO_SYSTEM_INIT * |
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| 51 | * * |
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| 52 | * If defined, the SystemInit() function will not be called. By default * |
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| 53 | * SystemInit() is called after reset to enable the clocks and memories to * |
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| 54 | * be initialised prior to any C startup initialisation. * |
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| 55 | * * |
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| 56 | * NO_VTOR_CONFIG * |
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| 57 | * * |
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| 58 | * If defined, the vector table offset register will not be configured. * |
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| 59 | * * |
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| 60 | * MEMORY_INIT * |
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| 61 | * * |
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| 62 | * If defined, the MemoryInit() function will be called. By default * |
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| 63 | * MemoryInit() is called after SystemInit() to enable an external memory * |
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| 64 | * controller. * |
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| 65 | * * |
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| 66 | * STACK_INIT_VAL * |
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| 67 | * * |
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| 68 | * If defined, specifies the initial stack pointer value. If undefined, * |
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| 69 | * the stack pointer will be initialised to point to the end of the * |
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| 70 | * RAM segment. * |
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| 71 | * * |
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| 72 | * VECTORS_IN_RAM * |
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| 73 | * * |
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| 74 | * If defined, the exception vectors will be copied from Flash to RAM. * |
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| 75 | * * |
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| 76 | *****************************************************************************/ |
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| 77 | |
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| 78 | .syntax unified |
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| 79 | |
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| 80 | .global Reset_Handler |
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| 81 | .extern _vectors |
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| 82 | |
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| 83 | .section .init, "ax" |
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| 84 | .thumb_func |
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| 85 | |
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| 86 | .equ VTOR_REG, 0xE000ED08 |
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| 87 | |
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| 88 | #ifndef STACK_INIT_VAL |
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| 89 | #define STACK_INIT_VAL __RAM_segment_end__ |
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| 90 | #endif |
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| 91 | |
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| 92 | Reset_Handler: |
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| 93 | #ifndef NO_STACK_INIT |
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| 94 | /* Initialize main stack */ |
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| 95 | ldr r0, =STACK_INIT_VAL |
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| 96 | ldr r1, =0x7 |
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| 97 | bics r0, r1 |
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| 98 | mov sp, r0 |
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| 99 | #endif |
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| 100 | |
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| 101 | #ifndef NO_SYSTEM_INIT |
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| 102 | /* Initialize system */ |
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| 103 | ldr r0, =SystemInit |
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| 104 | blx r0 |
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| 105 | .pushsection .init_array, "aw", %init_array |
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| 106 | .align 2 |
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| 107 | .word SystemCoreClockUpdate |
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| 108 | .popsection |
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| 109 | #endif |
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| 110 | |
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| 111 | #ifdef MEMORY_INIT |
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| 112 | ldr r0, =MemoryInit |
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| 113 | blx r0 |
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| 114 | #endif |
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| 115 | |
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| 116 | #ifdef VECTORS_IN_RAM |
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| 117 | /* Copy exception vectors into RAM */ |
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| 118 | ldr r0, =__vectors_start__ |
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| 119 | ldr r1, =__vectors_end__ |
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| 120 | ldr r2, =__vectors_ram_start__ |
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| 121 | 1: |
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| 122 | cmp r0, r1 |
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| 123 | beq 2f |
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| 124 | ldr r3, [r0] |
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| 125 | str r3, [r2] |
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| 126 | adds r0, r0, #4 |
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| 127 | adds r2, r2, #4 |
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| 128 | b 1b |
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| 129 | 2: |
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| 130 | #endif |
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| 131 | |
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| 132 | #ifndef NO_VTOR_CONFIG |
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| 133 | /* Configure vector table offset register */ |
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| 134 | ldr r0, =VTOR_REG |
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| 135 | #ifdef VECTORS_IN_RAM |
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| 136 | ldr r1, =_vectors_ram |
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| 137 | #else |
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| 138 | ldr r1, =_vectors |
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| 139 | #endif |
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| 140 | str r1, [r0] |
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| 141 | #endif |
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| 142 | |
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| 143 | /* Jump to program start */ |
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| 144 | b _start |
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| 145 | |
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| 146 | |
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