source: trunk/fw_g473rct/SES/STM32G4xx/Device/Source/system_stm32g4xx.c

Last change on this file was 20, checked in by f.jahn, 5 days ago

adc dma funktioniert und modbus funktioniert
File size: 10.8 KB
Line 
1/**
2  ******************************************************************************
3  * @file    system_stm32g4xx.c
4  * @author  MCD Application Team
5  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6  *
7  *   This file provides two functions and one global variable to be called from
8  *   user application:
9  *      - SystemInit(): This function is called at startup just after reset and
10  *                      before branch to main program. This call is made inside
11  *                      the "startup_stm32g4xx.s" file.
12  *
13  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14  *                                  by the user application to setup the SysTick
15  *                                  timer or configure other parameters.
16  *
17  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18  *                                 be called whenever the core clock is changed
19  *                                 during program execution.
20  *
21  *   After each device reset the HSI (16 MHz) is used as system clock source.
22  *   Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
23  *   configure the system clock before to branch to main program.
24  *
25  *   This file configures the system clock as follows:
26  *=============================================================================
27  *-----------------------------------------------------------------------------
28  *        System Clock source                    | HSI
29  *-----------------------------------------------------------------------------
30  *        SYSCLK(Hz)                             | 16000000
31  *-----------------------------------------------------------------------------
32  *        HCLK(Hz)                               | 16000000
33  *-----------------------------------------------------------------------------
34  *        AHB Prescaler                          | 1
35  *-----------------------------------------------------------------------------
36  *        APB1 Prescaler                         | 1
37  *-----------------------------------------------------------------------------
38  *        APB2 Prescaler                         | 1
39  *-----------------------------------------------------------------------------
40  *        PLL_M                                  | 1
41  *-----------------------------------------------------------------------------
42  *        PLL_N                                  | 16
43  *-----------------------------------------------------------------------------
44  *        PLL_P                                  | 7
45  *-----------------------------------------------------------------------------
46  *        PLL_Q                                  | 2
47  *-----------------------------------------------------------------------------
48  *        PLL_R                                  | 2
49  *-----------------------------------------------------------------------------
50  *        Require 48MHz for RNG                  | Disabled
51  *-----------------------------------------------------------------------------
52  *=============================================================================
53  ******************************************************************************
54  * @attention
55  *
56  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
57  * All rights reserved.</center></h2>
58  *
59  * This software component is licensed by ST under BSD 3-Clause license,
60  * the "License"; You may not use this file except in compliance with the
61  * License. You may obtain a copy of the License at:
62  *                        opensource.org/licenses/BSD-3-Clause
63  *
64  ******************************************************************************
65  */
66
67/** @addtogroup CMSIS
68  * @{
69  */
70
71/** @addtogroup stm32g4xx_system
72  * @{
73  */
74
75/** @addtogroup STM32G4xx_System_Private_Includes
76  * @{
77  */
78
79#include "stm32g4xx.h"
80
81#if !defined  (HSE_VALUE)
82  #define HSE_VALUE     24000000U /*!< Value of the External oscillator in Hz */
83#endif /* HSE_VALUE */
84
85#if !defined  (HSI_VALUE)
86  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
87#endif /* HSI_VALUE */
88
89/**
90  * @}
91  */
92
93/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
94  * @{
95  */
96
97/**
98  * @}
99  */
100
101/** @addtogroup STM32G4xx_System_Private_Defines
102  * @{
103  */
104
105/************************* Miscellaneous Configuration ************************/
106/* Note: Following vector table addresses must be defined in line with linker
107         configuration. */
108/*!< Uncomment the following line if you need to relocate the vector table
109     anywhere in Flash or Sram, else the vector table is kept at the automatic
110     remap of boot address selected */
111/* #define USER_VECT_TAB_ADDRESS */
112
113#if defined(USER_VECT_TAB_ADDRESS)
114/*!< Uncomment the following line if you need to relocate your vector Table
115     in Sram else user remap will be done in Flash. */
116/* #define VECT_TAB_SRAM */
117#if defined(VECT_TAB_SRAM)
118#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
119                                                     This value must be a multiple of 0x200. */
120#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
121                                                     This value must be a multiple of 0x200. */
122#else
123#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
124                                                     This value must be a multiple of 0x200. */
125#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
126                                                     This value must be a multiple of 0x200. */
127#endif /* VECT_TAB_SRAM */
128#endif /* USER_VECT_TAB_ADDRESS */
129/******************************************************************************/
130/**
131  * @}
132  */
133
134/** @addtogroup STM32G4xx_System_Private_Macros
135  * @{
136  */
137
138/**
139  * @}
140  */
141
142/** @addtogroup STM32G4xx_System_Private_Variables
143  * @{
144  */
145  /* The SystemCoreClock variable is updated in three ways:
146      1) by calling CMSIS function SystemCoreClockUpdate()
147      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
148      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
149         Note: If you use this function to configure the system clock; then there
150               is no need to call the 2 first functions listed above, since SystemCoreClock
151               variable is updated automatically.
152  */
153  uint32_t SystemCoreClock = HSI_VALUE;
154
155  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
156  const uint8_t APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
157
158/**
159  * @}
160  */
161
162/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
163  * @{
164  */
165
166/**
167  * @}
168  */
169
170/** @addtogroup STM32G4xx_System_Private_Functions
171  * @{
172  */
173
174/**
175  * @brief  Setup the microcontroller system.
176  * @param  None
177  * @retval None
178  */
179
180void SystemInit(void)
181{
182  /* FPU settings ------------------------------------------------------------*/
183  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
184    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
185  #endif
186
187  /* Configure the Vector Table location add offset address ------------------*/
188#if defined(USER_VECT_TAB_ADDRESS)
189  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
190#endif /* USER_VECT_TAB_ADDRESS */
191}
192
193/**
194  * @brief  Update SystemCoreClock variable according to Clock Register Values.
195  *         The SystemCoreClock variable contains the core clock (HCLK), it can
196  *         be used by the user application to setup the SysTick timer or configure
197  *         other parameters.
198  *
199  * @note   Each time the core clock (HCLK) changes, this function must be called
200  *         to update SystemCoreClock variable value. Otherwise, any configuration
201  *         based on this variable will be incorrect.
202  *
203  * @note   - The system frequency computed by this function is not the real
204  *           frequency in the chip. It is calculated based on the predefined
205  *           constant and the selected clock source:
206  *
207  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
208  *
209  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
210  *
211  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
212  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
213  *
214  *         (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
215  *              16 MHz) but the real value may vary depending on the variations
216  *              in voltage and temperature.
217  *
218  *         (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
219  *              24 MHz), user has to ensure that HSE_VALUE is same as the real
220  *              frequency of the crystal used. Otherwise, this function may
221  *              have wrong result.
222  *
223  *         - The result of this function could be not correct when using fractional
224  *           value for HSE crystal.
225  *
226  * @param  None
227  * @retval None
228  */
229void SystemCoreClockUpdate(void)
230{
231  uint32_t tmp, pllvco, pllr, pllsource, pllm;
232
233  /* Get SYSCLK source -------------------------------------------------------*/
234  switch (RCC->CFGR & RCC_CFGR_SWS)
235  {
236    case 0x04:  /* HSI used as system clock source */
237      SystemCoreClock = HSI_VALUE;
238      break;
239
240    case 0x08:  /* HSE used as system clock source */
241      SystemCoreClock = HSE_VALUE;
242      break;
243
244    case 0x0C:  /* PLL used as system clock  source */
245      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
246         SYSCLK = PLL_VCO / PLLR
247         */
248      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
249      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
250      if (pllsource == 0x02UL) /* HSI used as PLL clock source */
251      {
252        pllvco = (HSI_VALUE / pllm);
253      }
254      else                   /* HSE used as PLL clock source */
255      {
256        pllvco = (HSE_VALUE / pllm);
257      }
258      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
259      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
260      SystemCoreClock = pllvco/pllr;
261      break;
262
263    default:
264      break;
265  }
266  /* Compute HCLK clock frequency --------------------------------------------*/
267  /* Get HCLK prescaler */
268  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
269  /* HCLK clock frequency */
270  SystemCoreClock >>= tmp;
271}
272
273
274/**
275  * @}
276  */
277
278/**
279  * @}
280  */
281
282/**
283  * @}
284  */
285
286/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
287
Note: See TracBrowser for help on using the repository browser.