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cmsis_armcc.h @ 7

Last change on this file since 7 was 7, checked in by f.jahn, 5 months ago

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1	/************************************************************************//
2	* @file cmsis_armcc.h
3	* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4	* @version V5.3.2
5	* @date 27. May 2021
6	******************************************************************************/
7	/*
8	* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9	*
10	* SPDX-License-Identifier: Apache-2.0
11	*
12	* Licensed under the Apache License, Version 2.0 (the License); you may
13	* not use this file except in compliance with the License.
14	* You may obtain a copy of the License at
15	*
16	* www.apache.org/licenses/LICENSE-2.0
17	*
18	* Unless required by applicable law or agreed to in writing, software
19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21	* See the License for the specific language governing permissions and
22	* limitations under the License.
23	*/
24
25	#ifndef __CMSIS_ARMCC_H
26	#define __CMSIS_ARMCC_H
27
28
29	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30	#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31	#endif
32
33	/* CMSIS compiler control architecture macros */
34	#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) \|\| \
35	(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36	#define __ARM_ARCH_6M__ 1
37	#endif
38
39	#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40	#define __ARM_ARCH_7M__ 1
41	#endif
42
43	#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44	#define __ARM_ARCH_7EM__ 1
45	#endif
46
47	/* __ARM_ARCH_8M_BASE__ not applicable */
48	/* __ARM_ARCH_8M_MAIN__ not applicable */
49	/* __ARM_ARCH_8_1M_MAIN__ not applicable */
50
51	/* CMSIS compiler control DSP macros */
52	#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
53	#define __ARM_FEATURE_DSP 1
54	#endif
55
56	/* CMSIS compiler specific defines */
57	#ifndef __ASM
58	#define __ASM __asm
59	#endif
60	#ifndef __INLINE
61	#define __INLINE __inline
62	#endif
63	#ifndef __STATIC_INLINE
64	#define __STATIC_INLINE static __inline
65	#endif
66	#ifndef __STATIC_FORCEINLINE
67	#define __STATIC_FORCEINLINE static __forceinline
68	#endif
69	#ifndef __NO_RETURN
70	#define __NO_RETURN __declspec(noreturn)
71	#endif
72	#ifndef __USED
73	#define __USED __attribute__((used))
74	#endif
75	#ifndef __WEAK
76	#define __WEAK __attribute__((weak))
77	#endif
78	#ifndef __PACKED
79	#define __PACKED __attribute__((packed))
80	#endif
81	#ifndef __PACKED_STRUCT
82	#define __PACKED_STRUCT __packed struct
83	#endif
84	#ifndef __PACKED_UNION
85	#define __PACKED_UNION __packed union
86	#endif
87	#ifndef __UNALIGNED_UINT32 /* deprecated */
88	#define __UNALIGNED_UINT32(x) (((__packed uint32_t )(x)))
89	#endif
90	#ifndef __UNALIGNED_UINT16_WRITE
91	#define __UNALIGNED_UINT16_WRITE(addr, val) ((((__packed uint16_t )(addr))) = (val))
92	#endif
93	#ifndef __UNALIGNED_UINT16_READ
94	#define __UNALIGNED_UINT16_READ(addr) (((const __packed uint16_t )(addr)))
95	#endif
96	#ifndef __UNALIGNED_UINT32_WRITE
97	#define __UNALIGNED_UINT32_WRITE(addr, val) ((((__packed uint32_t )(addr))) = (val))
98	#endif
99	#ifndef __UNALIGNED_UINT32_READ
100	#define __UNALIGNED_UINT32_READ(addr) (((const __packed uint32_t )(addr)))
101	#endif
102	#ifndef __ALIGNED
103	#define __ALIGNED(x) __attribute__((aligned(x)))
104	#endif
105	#ifndef __RESTRICT
106	#define __RESTRICT __restrict
107	#endif
108	#ifndef __COMPILER_BARRIER
109	#define __COMPILER_BARRIER() __memory_changed()
110	#endif
111
112	/* ######################### Startup and Lowlevel Init ######################## */
113
114	#ifndef __PROGRAM_START
115	#define __PROGRAM_START __main
116	#endif
117
118	#ifndef __INITIAL_SP
119	#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
120	#endif
121
122	#ifndef __STACK_LIMIT
123	#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
124	#endif
125
126	#ifndef __VECTOR_TABLE
127	#define __VECTOR_TABLE __Vectors
128	#endif
129
130	#ifndef __VECTOR_TABLE_ATTRIBUTE
131	#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
132	#endif
133
134	/* ########################## Core Instruction Access ######################### */
135	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
136	Access to dedicated instructions
137	@{
138	*/
139
140	/**
141	\brief No Operation
142	\details No Operation does nothing. This instruction can be used for code alignment purposes.
143	*/
144	#define __NOP __nop
145
146
147	/**
148	\brief Wait For Interrupt
149	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
150	*/
151	#define __WFI __wfi
152
153
154	/**
155	\brief Wait For Event
156	\details Wait For Event is a hint instruction that permits the processor to enter
157	a low-power state until one of a number of events occurs.
158	*/
159	#define __WFE __wfe
160
161
162	/**
163	\brief Send Event
164	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
165	*/
166	#define __SEV __sev
167
168
169	/**
170	\brief Instruction Synchronization Barrier
171	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
172	so that all instructions following the ISB are fetched from cache or memory,
173	after the instruction has been completed.
174	*/
175	#define __ISB() __isb(0xF)
176
177	/**
178	\brief Data Synchronization Barrier
179	\details Acts as a special kind of Data Memory Barrier.
180	It completes when all explicit memory accesses before this instruction complete.
181	*/
182	#define __DSB() __dsb(0xF)
183
184	/**
185	\brief Data Memory Barrier
186	\details Ensures the apparent order of the explicit memory operations before
187	and after the instruction, without ensuring their completion.
188	*/
189	#define __DMB() __dmb(0xF)
190
191
192	/**
193	\brief Reverse byte order (32 bit)
194	\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
195	\param [in] value Value to reverse
196	\return Reversed value
197	*/
198	#define __REV __rev
199
200
201	/**
202	\brief Reverse byte order (16 bit)
203	\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
204	\param [in] value Value to reverse
205	\return Reversed value
206	*/
207	#ifndef __NO_EMBEDDED_ASM
208	__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
209	{
210	rev16 r0, r0
211	bx lr
212	}
213	#endif
214
215
216	/**
217	\brief Reverse byte order (16 bit)
218	\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
219	\param [in] value Value to reverse
220	\return Reversed value
221	*/
222	#ifndef __NO_EMBEDDED_ASM
223	__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
224	{
225	revsh r0, r0
226	bx lr
227	}
228	#endif
229
230
231	/**
232	\brief Rotate Right in unsigned value (32 bit)
233	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
234	\param [in] op1 Value to rotate
235	\param [in] op2 Number of Bits to rotate
236	\return Rotated value
237	*/
238	#define __ROR __ror
239
240
241	/**
242	\brief Breakpoint
243	\details Causes the processor to enter Debug state.
244	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
245	\param [in] value is ignored by the processor.
246	If required, a debugger can use it to store additional information about the breakpoint.
247	*/
248	#define __BKPT(value) __breakpoint(value)
249
250
251	/**
252	\brief Reverse bit order of value
253	\details Reverses the bit order of the given value.
254	\param [in] value Value to reverse
255	\return Reversed value
256	*/
257	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
258	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
259	#define __RBIT __rbit
260	#else
261	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
262	{
263	uint32_t result;
264	uint32_t s = (4U /sizeof(v)/ * 8U) - 1U; /* extra shift needed at end */
265
266	result = value; /* r will be reversed bits of v; first get LSB of v */
267	for (value >>= 1U; value != 0U; value >>= 1U)
268	{
269	result <<= 1U;
270	result \|= value & 1U;
271	s--;
272	}
273	result <<= s; /* shift when v's highest bits are zero */
274	return result;
275	}
276	#endif
277
278
279	/**
280	\brief Count leading zeros
281	\details Counts the number of leading zeros of a data value.
282	\param [in] value Value to count the leading zeros
283	\return number of leading zeros in value
284	*/
285	#define __CLZ __clz
286
287
288	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
289	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
290
291	/**
292	\brief LDR Exclusive (8 bit)
293	\details Executes a exclusive LDR instruction for 8 bit value.
294	\param [in] ptr Pointer to data
295	\return value of type uint8_t at (*ptr)
296	*/
297	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
298	#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
299	#else
300	#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
301	#endif
302
303
304	/**
305	\brief LDR Exclusive (16 bit)
306	\details Executes a exclusive LDR instruction for 16 bit values.
307	\param [in] ptr Pointer to data
308	\return value of type uint16_t at (*ptr)
309	*/
310	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
311	#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
312	#else
313	#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
314	#endif
315
316
317	/**
318	\brief LDR Exclusive (32 bit)
319	\details Executes a exclusive LDR instruction for 32 bit values.
320	\param [in] ptr Pointer to data
321	\return value of type uint32_t at (*ptr)
322	*/
323	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
324	#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
325	#else
326	#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
327	#endif
328
329
330	/**
331	\brief STR Exclusive (8 bit)
332	\details Executes a exclusive STR instruction for 8 bit values.
333	\param [in] value Value to store
334	\param [in] ptr Pointer to location
335	\return 0 Function succeeded
336	\return 1 Function failed
337	*/
338	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
339	#define __STREXB(value, ptr) __strex(value, ptr)
340	#else
341	#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
342	#endif
343
344
345	/**
346	\brief STR Exclusive (16 bit)
347	\details Executes a exclusive STR instruction for 16 bit values.
348	\param [in] value Value to store
349	\param [in] ptr Pointer to location
350	\return 0 Function succeeded
351	\return 1 Function failed
352	*/
353	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
354	#define __STREXH(value, ptr) __strex(value, ptr)
355	#else
356	#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
357	#endif
358
359
360	/**
361	\brief STR Exclusive (32 bit)
362	\details Executes a exclusive STR instruction for 32 bit values.
363	\param [in] value Value to store
364	\param [in] ptr Pointer to location
365	\return 0 Function succeeded
366	\return 1 Function failed
367	*/
368	#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
369	#define __STREXW(value, ptr) __strex(value, ptr)
370	#else
371	#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
372	#endif
373
374
375	/**
376	\brief Remove the exclusive lock
377	\details Removes the exclusive lock which is created by LDREX.
378	*/
379	#define __CLREX __clrex
380
381
382	/**
383	\brief Signed Saturate
384	\details Saturates a signed value.
385	\param [in] value Value to be saturated
386	\param [in] sat Bit position to saturate to (1..32)
387	\return Saturated value
388	*/
389	#define __SSAT __ssat
390
391
392	/**
393	\brief Unsigned Saturate
394	\details Saturates an unsigned value.
395	\param [in] value Value to be saturated
396	\param [in] sat Bit position to saturate to (0..31)
397	\return Saturated value
398	*/
399	#define __USAT __usat
400
401
402	/**
403	\brief Rotate Right with Extend (32 bit)
404	\details Moves each bit of a bitstring right by one bit.
405	The carry input is shifted in at the left end of the bitstring.
406	\param [in] value Value to rotate
407	\return Rotated value
408	*/
409	#ifndef __NO_EMBEDDED_ASM
410	__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
411	{
412	rrx r0, r0
413	bx lr
414	}
415	#endif
416
417
418	/**
419	\brief LDRT Unprivileged (8 bit)
420	\details Executes a Unprivileged LDRT instruction for 8 bit value.
421	\param [in] ptr Pointer to data
422	\return value of type uint8_t at (*ptr)
423	*/
424	#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
425
426
427	/**
428	\brief LDRT Unprivileged (16 bit)
429	\details Executes a Unprivileged LDRT instruction for 16 bit values.
430	\param [in] ptr Pointer to data
431	\return value of type uint16_t at (*ptr)
432	*/
433	#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
434
435
436	/**
437	\brief LDRT Unprivileged (32 bit)
438	\details Executes a Unprivileged LDRT instruction for 32 bit values.
439	\param [in] ptr Pointer to data
440	\return value of type uint32_t at (*ptr)
441	*/
442	#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
443
444
445	/**
446	\brief STRT Unprivileged (8 bit)
447	\details Executes a Unprivileged STRT instruction for 8 bit values.
448	\param [in] value Value to store
449	\param [in] ptr Pointer to location
450	*/
451	#define __STRBT(value, ptr) __strt(value, ptr)
452
453
454	/**
455	\brief STRT Unprivileged (16 bit)
456	\details Executes a Unprivileged STRT instruction for 16 bit values.
457	\param [in] value Value to store
458	\param [in] ptr Pointer to location
459	*/
460	#define __STRHT(value, ptr) __strt(value, ptr)
461
462
463	/**
464	\brief STRT Unprivileged (32 bit)
465	\details Executes a Unprivileged STRT instruction for 32 bit values.
466	\param [in] value Value to store
467	\param [in] ptr Pointer to location
468	*/
469	#define __STRT(value, ptr) __strt(value, ptr)
470
471	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
472	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
473
474	/**
475	\brief Signed Saturate
476	\details Saturates a signed value.
477	\param [in] value Value to be saturated
478	\param [in] sat Bit position to saturate to (1..32)
479	\return Saturated value
480	*/
481	__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
482	{
483	if ((sat >= 1U) && (sat <= 32U))
484	{
485	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
486	const int32_t min = -1 - max ;
487	if (val > max)
488	{
489	return max;
490	}
491	else if (val < min)
492	{
493	return min;
494	}
495	}
496	return val;
497	}
498
499	/**
500	\brief Unsigned Saturate
501	\details Saturates an unsigned value.
502	\param [in] value Value to be saturated
503	\param [in] sat Bit position to saturate to (0..31)
504	\return Saturated value
505	*/
506	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
507	{
508	if (sat <= 31U)
509	{
510	const uint32_t max = ((1U << sat) - 1U);
511	if (val > (int32_t)max)
512	{
513	return max;
514	}
515	else if (val < 0)
516	{
517	return 0U;
518	}
519	}
520	return (uint32_t)val;
521	}
522
523	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
524	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
525
526	/@}/ /* end of group CMSIS_Core_InstructionInterface */
527
528
529	/* ########################### Core Function Access ########################### */
530	/** \ingroup CMSIS_Core_FunctionInterface
531	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
532	@{
533	*/
534
535	/**
536	\brief Enable IRQ Interrupts
537	\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
538	Can only be executed in Privileged modes.
539	*/
540	/* intrinsic void __enable_irq(); */
541
542
543	/**
544	\brief Disable IRQ Interrupts
545	\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
546	Can only be executed in Privileged modes.
547	*/
548	/* intrinsic void __disable_irq(); */
549
550	/**
551	\brief Get Control Register
552	\details Returns the content of the Control Register.
553	\return Control Register value
554	*/
555	__STATIC_INLINE uint32_t __get_CONTROL(void)
556	{
557	register uint32_t __regControl __ASM("control");
558	return(__regControl);
559	}
560
561
562	/**
563	\brief Set Control Register
564	\details Writes the given value to the Control Register.
565	\param [in] control Control Register value to set
566	*/
567	__STATIC_INLINE void __set_CONTROL(uint32_t control)
568	{
569	register uint32_t __regControl __ASM("control");
570	__regControl = control;
571	__ISB();
572	}
573
574
575	/**
576	\brief Get IPSR Register
577	\details Returns the content of the IPSR Register.
578	\return IPSR Register value
579	*/
580	__STATIC_INLINE uint32_t __get_IPSR(void)
581	{
582	register uint32_t __regIPSR __ASM("ipsr");
583	return(__regIPSR);
584	}
585
586
587	/**
588	\brief Get APSR Register
589	\details Returns the content of the APSR Register.
590	\return APSR Register value
591	*/
592	__STATIC_INLINE uint32_t __get_APSR(void)
593	{
594	register uint32_t __regAPSR __ASM("apsr");
595	return(__regAPSR);
596	}
597
598
599	/**
600	\brief Get xPSR Register
601	\details Returns the content of the xPSR Register.
602	\return xPSR Register value
603	*/
604	__STATIC_INLINE uint32_t __get_xPSR(void)
605	{
606	register uint32_t __regXPSR __ASM("xpsr");
607	return(__regXPSR);
608	}
609
610
611	/**
612	\brief Get Process Stack Pointer
613	\details Returns the current value of the Process Stack Pointer (PSP).
614	\return PSP Register value
615	*/
616	__STATIC_INLINE uint32_t __get_PSP(void)
617	{
618	register uint32_t __regProcessStackPointer __ASM("psp");
619	return(__regProcessStackPointer);
620	}
621
622
623	/**
624	\brief Set Process Stack Pointer
625	\details Assigns the given value to the Process Stack Pointer (PSP).
626	\param [in] topOfProcStack Process Stack Pointer value to set
627	*/
628	__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
629	{
630	register uint32_t __regProcessStackPointer __ASM("psp");
631	__regProcessStackPointer = topOfProcStack;
632	}
633
634
635	/**
636	\brief Get Main Stack Pointer
637	\details Returns the current value of the Main Stack Pointer (MSP).
638	\return MSP Register value
639	*/
640	__STATIC_INLINE uint32_t __get_MSP(void)
641	{
642	register uint32_t __regMainStackPointer __ASM("msp");
643	return(__regMainStackPointer);
644	}
645
646
647	/**
648	\brief Set Main Stack Pointer
649	\details Assigns the given value to the Main Stack Pointer (MSP).
650	\param [in] topOfMainStack Main Stack Pointer value to set
651	*/
652	__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
653	{
654	register uint32_t __regMainStackPointer __ASM("msp");
655	__regMainStackPointer = topOfMainStack;
656	}
657
658
659	/**
660	\brief Get Priority Mask
661	\details Returns the current state of the priority mask bit from the Priority Mask Register.
662	\return Priority Mask value
663	*/
664	__STATIC_INLINE uint32_t __get_PRIMASK(void)
665	{
666	register uint32_t __regPriMask __ASM("primask");
667	return(__regPriMask);
668	}
669
670
671	/**
672	\brief Set Priority Mask
673	\details Assigns the given value to the Priority Mask Register.
674	\param [in] priMask Priority Mask
675	*/
676	__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
677	{
678	register uint32_t __regPriMask __ASM("primask");
679	__regPriMask = (priMask);
680	}
681
682
683	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
684	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
685
686	/**
687	\brief Enable FIQ
688	\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
689	Can only be executed in Privileged modes.
690	*/
691	#define __enable_fault_irq __enable_fiq
692
693
694	/**
695	\brief Disable FIQ
696	\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
697	Can only be executed in Privileged modes.
698	*/
699	#define __disable_fault_irq __disable_fiq
700
701
702	/**
703	\brief Get Base Priority
704	\details Returns the current value of the Base Priority register.
705	\return Base Priority register value
706	*/
707	__STATIC_INLINE uint32_t __get_BASEPRI(void)
708	{
709	register uint32_t __regBasePri __ASM("basepri");
710	return(__regBasePri);
711	}
712
713
714	/**
715	\brief Set Base Priority
716	\details Assigns the given value to the Base Priority register.
717	\param [in] basePri Base Priority value to set
718	*/
719	__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
720	{
721	register uint32_t __regBasePri __ASM("basepri");
722	__regBasePri = (basePri & 0xFFU);
723	}
724
725
726	/**
727	\brief Set Base Priority with condition
728	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
729	or the new value increases the BASEPRI priority level.
730	\param [in] basePri Base Priority value to set
731	*/
732	__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
733	{
734	register uint32_t __regBasePriMax __ASM("basepri_max");
735	__regBasePriMax = (basePri & 0xFFU);
736	}
737
738
739	/**
740	\brief Get Fault Mask
741	\details Returns the current value of the Fault Mask register.
742	\return Fault Mask register value
743	*/
744	__STATIC_INLINE uint32_t __get_FAULTMASK(void)
745	{
746	register uint32_t __regFaultMask __ASM("faultmask");
747	return(__regFaultMask);
748	}
749
750
751	/**
752	\brief Set Fault Mask
753	\details Assigns the given value to the Fault Mask register.
754	\param [in] faultMask Fault Mask value to set
755	*/
756	__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
757	{
758	register uint32_t __regFaultMask __ASM("faultmask");
759	__regFaultMask = (faultMask & (uint32_t)1U);
760	}
761
762	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
763	(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
764
765
766	/**
767	\brief Get FPSCR
768	\details Returns the current value of the Floating Point Status/Control register.
769	\return Floating Point Status/Control register value
770	*/
771	__STATIC_INLINE uint32_t __get_FPSCR(void)
772	{
773	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
774	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
775	register uint32_t __regfpscr __ASM("fpscr");
776	return(__regfpscr);
777	#else
778	return(0U);
779	#endif
780	}
781
782
783	/**
784	\brief Set FPSCR
785	\details Assigns the given value to the Floating Point Status/Control register.
786	\param [in] fpscr Floating Point Status/Control value to set
787	*/
788	__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
789	{
790	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
791	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
792	register uint32_t __regfpscr __ASM("fpscr");
793	__regfpscr = (fpscr);
794	#else
795	(void)fpscr;
796	#endif
797	}
798
799
800	/@} end of CMSIS_Core_RegAccFunctions /
801
802
803	/* ################### Compiler specific Intrinsics ########################### */
804	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
805	Access to dedicated SIMD instructions
806	@{
807	*/
808
809	#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
810
811	#define __SADD8 __sadd8
812	#define __QADD8 __qadd8
813	#define __SHADD8 __shadd8
814	#define __UADD8 __uadd8
815	#define __UQADD8 __uqadd8
816	#define __UHADD8 __uhadd8
817	#define __SSUB8 __ssub8
818	#define __QSUB8 __qsub8
819	#define __SHSUB8 __shsub8
820	#define __USUB8 __usub8
821	#define __UQSUB8 __uqsub8
822	#define __UHSUB8 __uhsub8
823	#define __SADD16 __sadd16
824	#define __QADD16 __qadd16
825	#define __SHADD16 __shadd16
826	#define __UADD16 __uadd16
827	#define __UQADD16 __uqadd16
828	#define __UHADD16 __uhadd16
829	#define __SSUB16 __ssub16
830	#define __QSUB16 __qsub16
831	#define __SHSUB16 __shsub16
832	#define __USUB16 __usub16
833	#define __UQSUB16 __uqsub16
834	#define __UHSUB16 __uhsub16
835	#define __SASX __sasx
836	#define __QASX __qasx
837	#define __SHASX __shasx
838	#define __UASX __uasx
839	#define __UQASX __uqasx
840	#define __UHASX __uhasx
841	#define __SSAX __ssax
842	#define __QSAX __qsax
843	#define __SHSAX __shsax
844	#define __USAX __usax
845	#define __UQSAX __uqsax
846	#define __UHSAX __uhsax
847	#define __USAD8 __usad8
848	#define __USADA8 __usada8
849	#define __SSAT16 __ssat16
850	#define __USAT16 __usat16
851	#define __UXTB16 __uxtb16
852	#define __UXTAB16 __uxtab16
853	#define __SXTB16 __sxtb16
854	#define __SXTAB16 __sxtab16
855	#define __SMUAD __smuad
856	#define __SMUADX __smuadx
857	#define __SMLAD __smlad
858	#define __SMLADX __smladx
859	#define __SMLALD __smlald
860	#define __SMLALDX __smlaldx
861	#define __SMUSD __smusd
862	#define __SMUSDX __smusdx
863	#define __SMLSD __smlsd
864	#define __SMLSDX __smlsdx
865	#define __SMLSLD __smlsld
866	#define __SMLSLDX __smlsldx
867	#define __SEL __sel
868	#define __QADD __qadd
869	#define __QSUB __qsub
870
871	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
872	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
873
874	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
875	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
876
877	#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
878	((int64_t)(ARG3) << 32U) ) >> 32U))
879
880	#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
881
882	#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
883
884	#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
885	/@} end of group CMSIS_SIMD_intrinsics /
886
887
888	#endif /* __CMSIS_ARMCC_H */

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source: trunk/firmware/Drivers/CMSIS/Include/cmsis_armcc.h @ 7

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