| 1 | /****************************************************************************** |
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| 2 | * @file pmu_armv8.h |
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| 3 | * @brief CMSIS PMU API for Armv8.1-M PMU |
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| 4 | * @version V1.0.1 |
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| 5 | * @date 15. April 2020 |
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| 6 | ******************************************************************************/ |
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| 7 | /* |
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| 8 | * Copyright (c) 2020 Arm Limited. All rights reserved. |
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| 9 | * |
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| 10 | * SPDX-License-Identifier: Apache-2.0 |
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| 11 | * |
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
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| 13 | * not use this file except in compliance with the License. |
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| 14 | * You may obtain a copy of the License at |
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| 15 | * |
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| 16 | * www.apache.org/licenses/LICENSE-2.0 |
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| 17 | * |
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| 18 | * Unless required by applicable law or agreed to in writing, software |
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 21 | * See the License for the specific language governing permissions and |
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| 22 | * limitations under the License. |
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| 23 | */ |
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| 24 | |
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| 25 | #if defined ( __ICCARM__ ) |
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| 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
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| 27 | #elif defined (__clang__) |
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| 28 | #pragma clang system_header /* treat file as system include file */ |
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| 29 | #endif |
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| 30 | |
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| 31 | #ifndef ARM_PMU_ARMV8_H |
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| 32 | #define ARM_PMU_ARMV8_H |
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| 33 | |
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| 34 | /** |
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| 35 | * \brief PMU Events |
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| 36 | * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. |
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| 37 | * */ |
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| 38 | |
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| 39 | #define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ |
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| 40 | #define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ |
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| 41 | #define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ |
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| 42 | #define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ |
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| 43 | #define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ |
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| 44 | #define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ |
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| 45 | #define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ |
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| 46 | #define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ |
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| 47 | #define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ |
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| 48 | #define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ |
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| 49 | #define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ |
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| 50 | #define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ |
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| 51 | #define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ |
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| 52 | #define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ |
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| 53 | #define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ |
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| 54 | #define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ |
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| 55 | #define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ |
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| 56 | #define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ |
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| 57 | #define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ |
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| 58 | #define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ |
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| 59 | #define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ |
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| 60 | #define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ |
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| 61 | #define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ |
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| 62 | #define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ |
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| 63 | #define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ |
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| 64 | #define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ |
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| 65 | #define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ |
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| 66 | #define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ |
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| 67 | #define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ |
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| 68 | #define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ |
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| 69 | #define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ |
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| 70 | #define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ |
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| 71 | #define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ |
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| 72 | #define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ |
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| 73 | #define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ |
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| 74 | #define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ |
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| 75 | #define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ |
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| 76 | #define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ |
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| 77 | #define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ |
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| 78 | #define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ |
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| 79 | #define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ |
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| 80 | #define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ |
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| 81 | #define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ |
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| 82 | #define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ |
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| 83 | #define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ |
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| 84 | #define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ |
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| 85 | #define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ |
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| 86 | #define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ |
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| 87 | #define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ |
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| 88 | #define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ |
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| 89 | #define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ |
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| 90 | #define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ |
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| 91 | #define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ |
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| 92 | #define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ |
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| 93 | #define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ |
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| 94 | #define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ |
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| 95 | #define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ |
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| 96 | #define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ |
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| 97 | #define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ |
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| 98 | #define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ |
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| 99 | #define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ |
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| 100 | #define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ |
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| 101 | #define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ |
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| 102 | #define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ |
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| 103 | #define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ |
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| 104 | #define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ |
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| 105 | #define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ |
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| 106 | #define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ |
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| 107 | #define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ |
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| 108 | #define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ |
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| 109 | #define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ |
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| 110 | #define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ |
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| 111 | #define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ |
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| 112 | #define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ |
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| 113 | #define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ |
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| 114 | #define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ |
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| 115 | #define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ |
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| 116 | #define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ |
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| 117 | #define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ |
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| 118 | #define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ |
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| 119 | #define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ |
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| 120 | #define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ |
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| 121 | #define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ |
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| 122 | #define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ |
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| 123 | #define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ |
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| 124 | #define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ |
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| 125 | #define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ |
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| 126 | #define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ |
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| 127 | #define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ |
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| 128 | #define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ |
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| 129 | #define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ |
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| 130 | #define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ |
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| 131 | #define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ |
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| 132 | #define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ |
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| 133 | #define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ |
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| 134 | #define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ |
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| 135 | #define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ |
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| 136 | #define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ |
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| 137 | #define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ |
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| 138 | #define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ |
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| 139 | #define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ |
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| 140 | #define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ |
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| 141 | #define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ |
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| 142 | #define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ |
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| 143 | #define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ |
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| 144 | #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ |
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| 145 | #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ |
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| 146 | #define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ |
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| 147 | #define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ |
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| 148 | #define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ |
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| 149 | #define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ |
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| 150 | #define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ |
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| 151 | #define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ |
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| 152 | #define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ |
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| 153 | #define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ |
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| 154 | #define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ |
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| 155 | #define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ |
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| 156 | #define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ |
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| 157 | #define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ |
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| 158 | #define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ |
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| 159 | #define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ |
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| 160 | #define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ |
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| 161 | #define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ |
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| 162 | #define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ |
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| 163 | #define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ |
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| 164 | #define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ |
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| 165 | #define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ |
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| 166 | #define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ |
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| 167 | #define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ |
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| 168 | #define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ |
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| 169 | #define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ |
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| 170 | |
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| 171 | /** \brief PMU Functions */ |
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| 172 | |
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| 173 | __STATIC_INLINE void ARM_PMU_Enable(void); |
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| 174 | __STATIC_INLINE void ARM_PMU_Disable(void); |
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| 175 | |
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| 176 | __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); |
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| 177 | |
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| 178 | __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); |
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| 179 | __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); |
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| 180 | |
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| 181 | __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); |
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| 182 | __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); |
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| 183 | |
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| 184 | __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); |
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| 185 | __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); |
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| 186 | |
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| 187 | __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); |
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| 188 | __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); |
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| 189 | |
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| 190 | __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); |
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| 191 | __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); |
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| 192 | |
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| 193 | __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); |
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| 194 | |
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| 195 | /** |
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| 196 | \brief Enable the PMU |
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| 197 | */ |
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| 198 | __STATIC_INLINE void ARM_PMU_Enable(void) |
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| 199 | { |
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| 200 | PMU->CTRL |= PMU_CTRL_ENABLE_Msk; |
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| 201 | } |
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| 202 | |
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| 203 | /** |
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| 204 | \brief Disable the PMU |
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| 205 | */ |
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| 206 | __STATIC_INLINE void ARM_PMU_Disable(void) |
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| 207 | { |
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| 208 | PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; |
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| 209 | } |
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| 210 | |
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| 211 | /** |
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| 212 | \brief Set event to count for PMU eventer counter |
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| 213 | \param [in] num Event counter (0-30) to configure |
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| 214 | \param [in] type Event to count |
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| 215 | */ |
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| 216 | __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) |
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| 217 | { |
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| 218 | PMU->EVTYPER[num] = type; |
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| 219 | } |
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| 220 | |
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| 221 | /** |
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| 222 | \brief Reset cycle counter |
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| 223 | */ |
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| 224 | __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) |
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| 225 | { |
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| 226 | PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; |
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| 227 | } |
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| 228 | |
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| 229 | /** |
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| 230 | \brief Reset all event counters |
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| 231 | */ |
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| 232 | __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) |
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| 233 | { |
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| 234 | PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; |
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| 235 | } |
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| 236 | |
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| 237 | /** |
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| 238 | \brief Enable counters |
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| 239 | \param [in] mask Counters to enable |
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| 240 | \note Enables one or more of the following: |
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| 241 | - event counters (0-30) |
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| 242 | - cycle counter |
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| 243 | */ |
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| 244 | __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) |
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| 245 | { |
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| 246 | PMU->CNTENSET = mask; |
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| 247 | } |
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| 248 | |
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| 249 | /** |
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| 250 | \brief Disable counters |
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| 251 | \param [in] mask Counters to enable |
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| 252 | \note Disables one or more of the following: |
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| 253 | - event counters (0-30) |
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| 254 | - cycle counter |
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| 255 | */ |
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| 256 | __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) |
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| 257 | { |
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| 258 | PMU->CNTENCLR = mask; |
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| 259 | } |
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| 260 | |
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| 261 | /** |
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| 262 | \brief Read cycle counter |
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| 263 | \return Cycle count |
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| 264 | */ |
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| 265 | __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) |
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| 266 | { |
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| 267 | return PMU->CCNTR; |
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| 268 | } |
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| 269 | |
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| 270 | /** |
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| 271 | \brief Read event counter |
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| 272 | \param [in] num Event counter (0-30) to read |
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| 273 | \return Event count |
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| 274 | */ |
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| 275 | __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) |
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| 276 | { |
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| 277 | return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; |
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| 278 | } |
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| 279 | |
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| 280 | /** |
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| 281 | \brief Read counter overflow status |
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| 282 | \return Counter overflow status bits for the following: |
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| 283 | - event counters (0-30) |
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| 284 | - cycle counter |
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| 285 | */ |
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| 286 | __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) |
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| 287 | { |
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| 288 | return PMU->OVSSET; |
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| 289 | } |
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| 290 | |
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| 291 | /** |
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| 292 | \brief Clear counter overflow status |
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| 293 | \param [in] mask Counter overflow status bits to clear |
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| 294 | \note Clears overflow status bits for one or more of the following: |
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| 295 | - event counters (0-30) |
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| 296 | - cycle counter |
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| 297 | */ |
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| 298 | __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) |
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| 299 | { |
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| 300 | PMU->OVSCLR = mask; |
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| 301 | } |
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| 302 | |
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| 303 | /** |
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| 304 | \brief Enable counter overflow interrupt request |
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| 305 | \param [in] mask Counter overflow interrupt request bits to set |
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| 306 | \note Sets overflow interrupt request bits for one or more of the following: |
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| 307 | - event counters (0-30) |
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| 308 | - cycle counter |
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| 309 | */ |
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| 310 | __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) |
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| 311 | { |
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| 312 | PMU->INTENSET = mask; |
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| 313 | } |
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| 314 | |
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| 315 | /** |
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| 316 | \brief Disable counter overflow interrupt request |
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| 317 | \param [in] mask Counter overflow interrupt request bits to clear |
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| 318 | \note Clears overflow interrupt request bits for one or more of the following: |
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| 319 | - event counters (0-30) |
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| 320 | - cycle counter |
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| 321 | */ |
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| 322 | __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) |
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| 323 | { |
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| 324 | PMU->INTENCLR = mask; |
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| 325 | } |
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| 326 | |
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| 327 | /** |
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| 328 | \brief Software increment event counter |
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| 329 | \param [in] mask Counters to increment |
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| 330 | \note Software increment bits for one or more event counters (0-30) |
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| 331 | */ |
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| 332 | __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) |
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| 333 | { |
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| 334 | PMU->SWINC = mask; |
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| 335 | } |
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| 336 | |
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| 337 | #endif |
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