1 | /********************************************************************* |
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2 | * SEGGER Microcontroller GmbH * |
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3 | * The Embedded Experts * |
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4 | ********************************************************************** |
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5 | * * |
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6 | * (c) 2014 - 2024 SEGGER Microcontroller GmbH * |
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7 | * * |
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8 | * www.segger.com Support: support@segger.com * |
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9 | * * |
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10 | ********************************************************************** |
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11 | * * |
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12 | * All rights reserved. * |
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13 | * * |
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14 | * Redistribution and use in source and binary forms, with or * |
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15 | * without modification, are permitted provided that the following * |
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16 | * condition is met: * |
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17 | * * |
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18 | * - Redistributions of source code must retain the above copyright * |
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19 | * notice, this condition and the following disclaimer. * |
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20 | * * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * |
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22 | * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * |
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23 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * |
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24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * |
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25 | * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * |
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26 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * |
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27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * |
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28 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * |
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29 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * |
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30 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * |
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31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * |
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32 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * |
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33 | * DAMAGE. * |
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34 | * * |
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35 | ********************************************************************** |
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36 | |
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37 | -------------------------- END-OF-HEADER ----------------------------- |
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38 | |
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39 | File : STM32C0xx_Startup.s |
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40 | Purpose : Startup and exception handlers for STM32C0xx devices. |
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41 | |
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42 | Additional information: |
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43 | Preprocessor Definitions |
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44 | __NO_SYSTEM_INIT |
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45 | If defined, |
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46 | SystemInit is not called. |
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47 | If not defined, |
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48 | SystemInit is called. |
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49 | SystemInit is usually supplied by the CMSIS files. |
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50 | This file declares a weak implementation as fallback. |
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51 | |
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52 | __NO_SYSTEM_CLK_UPDATE |
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53 | If defined, |
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54 | SystemCoreClockUpdate is not automatically called. |
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55 | Should be defined if SystemCoreClockUpdate must not be called before main(). |
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56 | If not defined, |
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57 | SystemCoreClockUpdate is called before the application entry point. |
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58 | |
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59 | __MEMORY_INIT |
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60 | If defined, |
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61 | MemoryInit is called after SystemInit. |
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62 | void MemoryInit(void) can be implemented to enable external |
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63 | memory controllers. |
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64 | |
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65 | __VECTORS_IN_RAM |
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66 | If defined, |
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67 | the vector table will be copied from Flash to RAM, |
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68 | and the vector table offset register is adjusted. |
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69 | |
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70 | __VTOR_CONFIG |
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71 | If defined, |
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72 | the vector table offset register is set to point to the |
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73 | application's vector table. |
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74 | |
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75 | __NO_FPU_ENABLE |
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76 | If defined, the FPU is explicitly not enabled, |
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77 | even if the compiler could use floating point operations. |
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78 | |
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79 | __SOFTFP__ |
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80 | Defined by the build system. |
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81 | If not defined, the FPU is enabled for floating point operations. |
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82 | */ |
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83 | |
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84 | .syntax unified |
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85 | |
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86 | |
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87 | /********************************************************************* |
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88 | * |
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89 | * Global functions |
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90 | * |
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91 | ********************************************************************** |
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92 | */ |
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93 | /********************************************************************* |
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94 | * |
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95 | * Reset_Handler |
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96 | * |
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97 | * Function description |
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98 | * Exception handler for reset. |
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99 | * Generic bringup of a Cortex-M system. |
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100 | * |
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101 | * Additional information |
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102 | * The stack pointer is expected to be initialized by hardware, |
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103 | * i.e. read from vectortable[0]. |
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104 | * For manual initialization add |
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105 | * ldr R0, =__stack_end__ |
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106 | * mov SP, R0 |
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107 | */ |
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108 | .global reset_handler |
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109 | .global Reset_Handler |
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110 | .equ reset_handler, Reset_Handler |
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111 | .section .init.Reset_Handler, "ax" |
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112 | .balign 2 |
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113 | .thumb_func |
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114 | Reset_Handler: |
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115 | #ifdef __SEGGER_STOP |
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116 | .extern __SEGGER_STOP_Limit_MSP |
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117 | // |
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118 | // Initialize main stack limit to 0 to disable stack checks before runtime init |
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119 | // |
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120 | movs R0, #0 |
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121 | ldr R1, =__SEGGER_STOP_Limit_MSP |
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122 | str R0, [R1] |
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123 | #endif |
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124 | #ifndef __NO_SYSTEM_INIT |
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125 | // |
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126 | // Call SystemInit |
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127 | // |
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128 | bl SystemInit |
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129 | #endif |
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130 | #ifdef __MEMORY_INIT |
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131 | // |
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132 | // Call MemoryInit |
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133 | // |
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134 | bl MemoryInit |
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135 | #endif |
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136 | #ifdef __VECTORS_IN_RAM |
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137 | // |
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138 | // Copy vector table (from Flash) to RAM |
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139 | // |
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140 | ldr R0, =__vectors_start__ |
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141 | ldr R1, =__vectors_end__ |
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142 | ldr R2, =__vectors_ram_start__ |
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143 | 1: |
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144 | cmp R0, R1 |
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145 | beq 2f |
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146 | ldr R3, [R0] |
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147 | str R3, [R2] |
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148 | adds R0, R0, #4 |
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149 | adds R2, R2, #4 |
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150 | b 1b |
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151 | 2: |
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152 | #endif |
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153 | |
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154 | #if defined(__VTOR_CONFIG) || defined(__VECTORS_IN_RAM) |
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155 | // |
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156 | // Configure vector table offset register |
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157 | // |
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158 | #ifdef __ARM_ARCH_6M__ |
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159 | ldr R0, =0xE000ED08 // VTOR_REG |
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160 | #else |
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161 | movw R0, 0xED08 // VTOR_REG |
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162 | movt R0, 0xE000 |
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163 | #endif |
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164 | #ifdef __VECTORS_IN_RAM |
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165 | ldr R1, =_vectors_ram |
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166 | #else |
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167 | ldr R1, =_vectors |
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168 | #endif |
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169 | str R1, [R0] |
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170 | #endif |
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171 | #if !defined(__SOFTFP__) && !defined(__NO_FPU_ENABLE) |
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172 | // |
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173 | // Enable CP11 and CP10 with CPACR |= (0xf<<20) |
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174 | // |
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175 | movw R0, 0xED88 // CPACR |
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176 | movt R0, 0xE000 |
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177 | ldr R1, [R0] |
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178 | orrs R1, R1, #(0xf << 20) |
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179 | str R1, [R0] |
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180 | #endif |
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181 | // |
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182 | // Call runtime initialization, which calls main(). |
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183 | // |
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184 | bl _start |
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185 | |
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186 | // |
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187 | // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, |
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188 | // when there is no strong definition of SystemInit. |
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189 | // |
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190 | .weak SystemInit |
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191 | // |
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192 | // Place SystemCoreClockUpdate in .init_array |
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193 | // to be called after runtime initialization |
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194 | // |
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195 | #if !defined(__NO_SYSTEM_INIT) && !defined(__NO_SYSTEM_CLK_UPDATE) |
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196 | .section .init_array, "aw" |
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197 | .balign 4 |
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198 | .word SystemCoreClockUpdate |
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199 | #endif |
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200 | |
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201 | /********************************************************************* |
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202 | * |
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203 | * HardFault_Handler |
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204 | * |
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205 | * Function description |
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206 | * Simple exception handler for HardFault. |
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207 | * In case of a HardFault caused by BKPT instruction without |
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208 | * debugger attached, return execution, otherwise stay in loop. |
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209 | * |
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210 | * Additional information |
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211 | * The stack pointer is expected to be initialized by hardware, |
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212 | * i.e. read from vectortable[0]. |
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213 | * For manual initialization add |
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214 | * ldr R0, =__stack_end__ |
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215 | * mov SP, R0 |
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216 | */ |
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217 | |
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218 | #undef L |
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219 | #define L(label) .LHardFault_Handler_##label |
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220 | |
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221 | .weak HardFault_Handler |
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222 | .section .init.HardFault_Handler, "ax" |
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223 | .balign 2 |
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224 | .thumb_func |
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225 | HardFault_Handler: |
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226 | // |
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227 | // Check if HardFault is caused by BKPT instruction |
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228 | // |
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229 | ldr R1, =0xE000ED2C // Load NVIC_HFSR |
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230 | ldr R2, [R1] |
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231 | cmp R2, #0 // Check NVIC_HFSR[31] |
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232 | |
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233 | L(hfLoop): |
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234 | bmi L(hfLoop) // Not set? Stay in HardFault Handler. |
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235 | // |
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236 | // Continue execution after BKPT instruction |
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237 | // |
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238 | #if defined(__thumb__) && !defined(__thumb2__) |
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239 | movs R0, #4 |
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240 | mov R1, LR |
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241 | tst R0, R1 // Check EXC_RETURN in Link register bit 2. |
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242 | bne L(Uses_PSP) |
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243 | mrs R0, MSP // Stacking was using MSP. |
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244 | b L(Pass_StackPtr) |
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245 | L(Uses_PSP): |
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246 | mrs R0, PSP // Stacking was using PSP. |
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247 | L(Pass_StackPtr): |
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248 | #else |
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249 | tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack |
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250 | ite eq |
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251 | mrseq R0, MSP // Frame stored on MSP |
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252 | mrsne R0, PSP // Frame stored on PSP |
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253 | #endif |
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254 | // |
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255 | // Reset HardFault Status |
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256 | // |
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257 | #if defined(__thumb__) && !defined(__thumb2__) |
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258 | movs R3, #1 |
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259 | lsls R3, R3, #31 |
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260 | orrs R2, R3 |
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261 | str R2, [R1] |
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262 | #else |
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263 | orr R2, R2, #0x80000000 |
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264 | str R2, [R1] |
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265 | #endif |
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266 | // |
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267 | // Adjust return address |
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268 | // |
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269 | ldr R1, [R0, #24] // Get stored PC from stack |
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270 | adds R1, #2 // Adjust PC by 2 to skip current BKPT |
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271 | str R1, [R0, #24] // Write back adjusted PC to stack |
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272 | // |
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273 | bx LR // Return |
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274 | |
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275 | /*************************** End of file ****************************/ |
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