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cmsis_iccarm.h @ 9

Last change on this file since 9 was 7, checked in by f.jahn, 5 months ago

File size: 28.4 KB

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1	/************************************************************************//
2	* @file cmsis_iccarm.h
3	* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4	* @version V5.3.0
5	* @date 14. April 2021
6	******************************************************************************/
7
8	//------------------------------------------------------------------------------
9	//
10	// Copyright (c) 2017-2021 IAR Systems
11	// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
12	//
13	// SPDX-License-Identifier: Apache-2.0
14	//
15	// Licensed under the Apache License, Version 2.0 (the "License")
16	// you may not use this file except in compliance with the License.
17	// You may obtain a copy of the License at
18	// http://www.apache.org/licenses/LICENSE-2.0
19	//
20	// Unless required by applicable law or agreed to in writing, software
21	// distributed under the License is distributed on an "AS IS" BASIS,
22	// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23	// See the License for the specific language governing permissions and
24	// limitations under the License.
25	//
26	//------------------------------------------------------------------------------
27
28
29	#ifndef __CMSIS_ICCARM_H__
30	#define __CMSIS_ICCARM_H__
31
32	#ifndef __ICCARM__
33	#error This file should only be compiled by ICCARM
34	#endif
35
36	#pragma system_include
37
38	#define __IAR_FT _Pragma("inline=forced") __intrinsic
39
40	#if (__VER__ >= 8000000)
41	#define __ICCARM_V8 1
42	#else
43	#define __ICCARM_V8 0
44	#endif
45
46	#ifndef __ALIGNED
47	#if __ICCARM_V8
48	#define __ALIGNED(x) __attribute__((aligned(x)))
49	#elif (__VER__ >= 7080000)
50	/* Needs IAR language extensions */
51	#define __ALIGNED(x) __attribute__((aligned(x)))
52	#else
53	#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54	#define __ALIGNED(x)
55	#endif
56	#endif
57
58
59	/* Define compiler macros for CPU architecture, used in CMSIS 5.
60	*/
61	#if __ARM_ARCH_6M__ \|\| __ARM_ARCH_7M__ \|\| __ARM_ARCH_7EM__ \|\| __ARM_ARCH_8M_BASE__ \|\| __ARM_ARCH_8M_MAIN__
62	/* Macros already defined */
63	#else
64	#if defined(__ARM8M_MAINLINE__) \|\| defined(__ARM8EM_MAINLINE__)
65	#define __ARM_ARCH_8M_MAIN__ 1
66	#elif defined(__ARM8M_BASELINE__)
67	#define __ARM_ARCH_8M_BASE__ 1
68	#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69	#if __ARM_ARCH == 6
70	#define __ARM_ARCH_6M__ 1
71	#elif __ARM_ARCH == 7
72	#if __ARM_FEATURE_DSP
73	#define __ARM_ARCH_7EM__ 1
74	#else
75	#define __ARM_ARCH_7M__ 1
76	#endif
77	#endif /* __ARM_ARCH */
78	#endif /* __ARM_ARCH_PROFILE == 'M' */
79	#endif
80
81	/* Alternativ core deduction for older ICCARM's */
82	#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83	!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84	#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85	#define __ARM_ARCH_6M__ 1
86	#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87	#define __ARM_ARCH_7M__ 1
88	#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89	#define __ARM_ARCH_7EM__ 1
90	#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91	#define __ARM_ARCH_8M_BASE__ 1
92	#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93	#define __ARM_ARCH_8M_MAIN__ 1
94	#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95	#define __ARM_ARCH_8M_MAIN__ 1
96	#else
97	#error "Unknown target."
98	#endif
99	#endif
100
101
102
103	#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104	#define __IAR_M0_FAMILY 1
105	#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106	#define __IAR_M0_FAMILY 1
107	#else
108	#define __IAR_M0_FAMILY 0
109	#endif
110
111
112	#ifndef __ASM
113	#define __ASM __asm
114	#endif
115
116	#ifndef __COMPILER_BARRIER
117	#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118	#endif
119
120	#ifndef __INLINE
121	#define __INLINE inline
122	#endif
123
124	#ifndef __NO_RETURN
125	#if __ICCARM_V8
126	#define __NO_RETURN __attribute__((__noreturn__))
127	#else
128	#define __NO_RETURN _Pragma("object_attribute=__noreturn")
129	#endif
130	#endif
131
132	#ifndef __PACKED
133	#if __ICCARM_V8
134	#define __PACKED __attribute__((packed, aligned(1)))
135	#else
136	/* Needs IAR language extensions */
137	#define __PACKED __packed
138	#endif
139	#endif
140
141	#ifndef __PACKED_STRUCT
142	#if __ICCARM_V8
143	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144	#else
145	/* Needs IAR language extensions */
146	#define __PACKED_STRUCT __packed struct
147	#endif
148	#endif
149
150	#ifndef __PACKED_UNION
151	#if __ICCARM_V8
152	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
153	#else
154	/* Needs IAR language extensions */
155	#define __PACKED_UNION __packed union
156	#endif
157	#endif
158
159	#ifndef __RESTRICT
160	#if __ICCARM_V8
161	#define __RESTRICT __restrict
162	#else
163	/* Needs IAR language extensions */
164	#define __RESTRICT restrict
165	#endif
166	#endif
167
168	#ifndef __STATIC_INLINE
169	#define __STATIC_INLINE static inline
170	#endif
171
172	#ifndef __FORCEINLINE
173	#define __FORCEINLINE _Pragma("inline=forced")
174	#endif
175
176	#ifndef __STATIC_FORCEINLINE
177	#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178	#endif
179
180	#ifndef __UNALIGNED_UINT16_READ
181	#pragma language=save
182	#pragma language=extended
183	__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
184	{
185	return (__packed uint16_t)(ptr);
186	}
187	#pragma language=restore
188	#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
189	#endif
190
191
192	#ifndef __UNALIGNED_UINT16_WRITE
193	#pragma language=save
194	#pragma language=extended
195	__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
196	{
197	(__packed uint16_t)(ptr) = val;;
198	}
199	#pragma language=restore
200	#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201	#endif
202
203	#ifndef __UNALIGNED_UINT32_READ
204	#pragma language=save
205	#pragma language=extended
206	__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
207	{
208	return (__packed uint32_t)(ptr);
209	}
210	#pragma language=restore
211	#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212	#endif
213
214	#ifndef __UNALIGNED_UINT32_WRITE
215	#pragma language=save
216	#pragma language=extended
217	__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
218	{
219	(__packed uint32_t)(ptr) = val;;
220	}
221	#pragma language=restore
222	#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223	#endif
224
225	#ifndef __UNALIGNED_UINT32 /* deprecated */
226	#pragma language=save
227	#pragma language=extended
228	__packed struct __iar_u32 { uint32_t v; };
229	#pragma language=restore
230	#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
231	#endif
232
233	#ifndef __USED
234	#if __ICCARM_V8
235	#define __USED __attribute__((used))
236	#else
237	#define __USED _Pragma("__root")
238	#endif
239	#endif
240
241	#undef __WEAK /* undo the definition from DLib_Defaults.h */
242	#ifndef __WEAK
243	#if __ICCARM_V8
244	#define __WEAK __attribute__((weak))
245	#else
246	#define __WEAK _Pragma("__weak")
247	#endif
248	#endif
249
250	#ifndef __PROGRAM_START
251	#define __PROGRAM_START __iar_program_start
252	#endif
253
254	#ifndef __INITIAL_SP
255	#define __INITIAL_SP CSTACK$$Limit
256	#endif
257
258	#ifndef __STACK_LIMIT
259	#define __STACK_LIMIT CSTACK$$Base
260	#endif
261
262	#ifndef __VECTOR_TABLE
263	#define __VECTOR_TABLE __vector_table
264	#endif
265
266	#ifndef __VECTOR_TABLE_ATTRIBUTE
267	#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
268	#endif
269
270	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
271	#ifndef __STACK_SEAL
272	#define __STACK_SEAL STACKSEAL$$Base
273	#endif
274
275	#ifndef __TZ_STACK_SEAL_SIZE
276	#define __TZ_STACK_SEAL_SIZE 8U
277	#endif
278
279	#ifndef __TZ_STACK_SEAL_VALUE
280	#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
281	#endif
282
283	__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
284	((uint64_t )stackTop) = __TZ_STACK_SEAL_VALUE;
285	}
286	#endif
287
288	#ifndef __ICCARM_INTRINSICS_VERSION__
289	#define __ICCARM_INTRINSICS_VERSION__ 0
290	#endif
291
292	#if __ICCARM_INTRINSICS_VERSION__ == 2
293
294	#if defined(__CLZ)
295	#undef __CLZ
296	#endif
297	#if defined(__REVSH)
298	#undef __REVSH
299	#endif
300	#if defined(__RBIT)
301	#undef __RBIT
302	#endif
303	#if defined(__SSAT)
304	#undef __SSAT
305	#endif
306	#if defined(__USAT)
307	#undef __USAT
308	#endif
309
310	#include "iccarm_builtin.h"
311
312	#define __disable_fault_irq __iar_builtin_disable_fiq
313	#define __disable_irq __iar_builtin_disable_interrupt
314	#define __enable_fault_irq __iar_builtin_enable_fiq
315	#define __enable_irq __iar_builtin_enable_interrupt
316	#define __arm_rsr __iar_builtin_rsr
317	#define __arm_wsr __iar_builtin_wsr
318
319
320	#define __get_APSR() (__arm_rsr("APSR"))
321	#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
322	#define __get_CONTROL() (__arm_rsr("CONTROL"))
323	#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
324
325	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
326	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
327	#define __get_FPSCR() (__arm_rsr("FPSCR"))
328	#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
329	#else
330	#define __get_FPSCR() ( 0 )
331	#define __set_FPSCR(VALUE) ((void)VALUE)
332	#endif
333
334	#define __get_IPSR() (__arm_rsr("IPSR"))
335	#define __get_MSP() (__arm_rsr("MSP"))
336	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
337	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
338	// without main extensions, the non-secure MSPLIM is RAZ/WI
339	#define __get_MSPLIM() (0U)
340	#else
341	#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
342	#endif
343	#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
344	#define __get_PSP() (__arm_rsr("PSP"))
345
346	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
347	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
348	// without main extensions, the non-secure PSPLIM is RAZ/WI
349	#define __get_PSPLIM() (0U)
350	#else
351	#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
352	#endif
353
354	#define __get_xPSR() (__arm_rsr("xPSR"))
355
356	#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
357	#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
358
359	__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
360	{
361	__arm_wsr("CONTROL", control);
362	__iar_builtin_ISB();
363	}
364
365	#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
366	#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
367
368	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
369	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
370	// without main extensions, the non-secure MSPLIM is RAZ/WI
371	#define __set_MSPLIM(VALUE) ((void)(VALUE))
372	#else
373	#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
374	#endif
375	#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
376	#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
377	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
378	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
379	// without main extensions, the non-secure PSPLIM is RAZ/WI
380	#define __set_PSPLIM(VALUE) ((void)(VALUE))
381	#else
382	#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
383	#endif
384
385	#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
386
387	__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
388	{
389	__arm_wsr("CONTROL_NS", control);
390	__iar_builtin_ISB();
391	}
392
393	#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
394	#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
395	#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
396	#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
397	#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
398	#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
399	#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
400	#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
401	#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
402	#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
403	#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
404	#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
405
406	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
407	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
408	// without main extensions, the non-secure PSPLIM is RAZ/WI
409	#define __TZ_get_PSPLIM_NS() (0U)
410	#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
411	#else
412	#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
413	#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
414	#endif
415
416	#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
417	#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
418
419	#define __NOP __iar_builtin_no_operation
420
421	#define __CLZ __iar_builtin_CLZ
422	#define __CLREX __iar_builtin_CLREX
423
424	#define __DMB __iar_builtin_DMB
425	#define __DSB __iar_builtin_DSB
426	#define __ISB __iar_builtin_ISB
427
428	#define __LDREXB __iar_builtin_LDREXB
429	#define __LDREXH __iar_builtin_LDREXH
430	#define __LDREXW __iar_builtin_LDREX
431
432	#define __RBIT __iar_builtin_RBIT
433	#define __REV __iar_builtin_REV
434	#define __REV16 __iar_builtin_REV16
435
436	__IAR_FT int16_t __REVSH(int16_t val)
437	{
438	return (int16_t) __iar_builtin_REVSH(val);
439	}
440
441	#define __ROR __iar_builtin_ROR
442	#define __RRX __iar_builtin_RRX
443
444	#define __SEV __iar_builtin_SEV
445
446	#if !__IAR_M0_FAMILY
447	#define __SSAT __iar_builtin_SSAT
448	#endif
449
450	#define __STREXB __iar_builtin_STREXB
451	#define __STREXH __iar_builtin_STREXH
452	#define __STREXW __iar_builtin_STREX
453
454	#if !__IAR_M0_FAMILY
455	#define __USAT __iar_builtin_USAT
456	#endif
457
458	#define __WFE __iar_builtin_WFE
459	#define __WFI __iar_builtin_WFI
460
461	#if __ARM_MEDIA__
462	#define __SADD8 __iar_builtin_SADD8
463	#define __QADD8 __iar_builtin_QADD8
464	#define __SHADD8 __iar_builtin_SHADD8
465	#define __UADD8 __iar_builtin_UADD8
466	#define __UQADD8 __iar_builtin_UQADD8
467	#define __UHADD8 __iar_builtin_UHADD8
468	#define __SSUB8 __iar_builtin_SSUB8
469	#define __QSUB8 __iar_builtin_QSUB8
470	#define __SHSUB8 __iar_builtin_SHSUB8
471	#define __USUB8 __iar_builtin_USUB8
472	#define __UQSUB8 __iar_builtin_UQSUB8
473	#define __UHSUB8 __iar_builtin_UHSUB8
474	#define __SADD16 __iar_builtin_SADD16
475	#define __QADD16 __iar_builtin_QADD16
476	#define __SHADD16 __iar_builtin_SHADD16
477	#define __UADD16 __iar_builtin_UADD16
478	#define __UQADD16 __iar_builtin_UQADD16
479	#define __UHADD16 __iar_builtin_UHADD16
480	#define __SSUB16 __iar_builtin_SSUB16
481	#define __QSUB16 __iar_builtin_QSUB16
482	#define __SHSUB16 __iar_builtin_SHSUB16
483	#define __USUB16 __iar_builtin_USUB16
484	#define __UQSUB16 __iar_builtin_UQSUB16
485	#define __UHSUB16 __iar_builtin_UHSUB16
486	#define __SASX __iar_builtin_SASX
487	#define __QASX __iar_builtin_QASX
488	#define __SHASX __iar_builtin_SHASX
489	#define __UASX __iar_builtin_UASX
490	#define __UQASX __iar_builtin_UQASX
491	#define __UHASX __iar_builtin_UHASX
492	#define __SSAX __iar_builtin_SSAX
493	#define __QSAX __iar_builtin_QSAX
494	#define __SHSAX __iar_builtin_SHSAX
495	#define __USAX __iar_builtin_USAX
496	#define __UQSAX __iar_builtin_UQSAX
497	#define __UHSAX __iar_builtin_UHSAX
498	#define __USAD8 __iar_builtin_USAD8
499	#define __USADA8 __iar_builtin_USADA8
500	#define __SSAT16 __iar_builtin_SSAT16
501	#define __USAT16 __iar_builtin_USAT16
502	#define __UXTB16 __iar_builtin_UXTB16
503	#define __UXTAB16 __iar_builtin_UXTAB16
504	#define __SXTB16 __iar_builtin_SXTB16
505	#define __SXTAB16 __iar_builtin_SXTAB16
506	#define __SMUAD __iar_builtin_SMUAD
507	#define __SMUADX __iar_builtin_SMUADX
508	#define __SMMLA __iar_builtin_SMMLA
509	#define __SMLAD __iar_builtin_SMLAD
510	#define __SMLADX __iar_builtin_SMLADX
511	#define __SMLALD __iar_builtin_SMLALD
512	#define __SMLALDX __iar_builtin_SMLALDX
513	#define __SMUSD __iar_builtin_SMUSD
514	#define __SMUSDX __iar_builtin_SMUSDX
515	#define __SMLSD __iar_builtin_SMLSD
516	#define __SMLSDX __iar_builtin_SMLSDX
517	#define __SMLSLD __iar_builtin_SMLSLD
518	#define __SMLSLDX __iar_builtin_SMLSLDX
519	#define __SEL __iar_builtin_SEL
520	#define __QADD __iar_builtin_QADD
521	#define __QSUB __iar_builtin_QSUB
522	#define __PKHBT __iar_builtin_PKHBT
523	#define __PKHTB __iar_builtin_PKHTB
524	#endif
525
526	#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
527
528	#if __IAR_M0_FAMILY
529	/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
530	#define __CLZ __cmsis_iar_clz_not_active
531	#define __SSAT __cmsis_iar_ssat_not_active
532	#define __USAT __cmsis_iar_usat_not_active
533	#define __RBIT __cmsis_iar_rbit_not_active
534	#define __get_APSR __cmsis_iar_get_APSR_not_active
535	#endif
536
537
538	#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
539	(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
540	#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
541	#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
542	#endif
543
544	#ifdef __INTRINSICS_INCLUDED
545	#error intrinsics.h is already included previously!
546	#endif
547
548	#include <intrinsics.h>
549
550	#if __IAR_M0_FAMILY
551	/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
552	#undef __CLZ
553	#undef __SSAT
554	#undef __USAT
555	#undef __RBIT
556	#undef __get_APSR
557
558	__STATIC_INLINE uint8_t __CLZ(uint32_t data)
559	{
560	if (data == 0U) { return 32U; }
561
562	uint32_t count = 0U;
563	uint32_t mask = 0x80000000U;
564
565	while ((data & mask) == 0U)
566	{
567	count += 1U;
568	mask = mask >> 1U;
569	}
570	return count;
571	}
572
573	__STATIC_INLINE uint32_t __RBIT(uint32_t v)
574	{
575	uint8_t sc = 31U;
576	uint32_t r = v;
577	for (v >>= 1U; v; v >>= 1U)
578	{
579	r <<= 1U;
580	r \|= v & 1U;
581	sc--;
582	}
583	return (r << sc);
584	}
585
586	__STATIC_INLINE uint32_t __get_APSR(void)
587	{
588	uint32_t res;
589	__asm("MRS %0,APSR" : "=r" (res));
590	return res;
591	}
592
593	#endif
594
595	#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
596	(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
597	#undef __get_FPSCR
598	#undef __set_FPSCR
599	#define __get_FPSCR() (0)
600	#define __set_FPSCR(VALUE) ((void)VALUE)
601	#endif
602
603	#pragma diag_suppress=Pe940
604	#pragma diag_suppress=Pe177
605
606	#define __enable_irq __enable_interrupt
607	#define __disable_irq __disable_interrupt
608	#define __NOP __no_operation
609
610	#define __get_xPSR __get_PSR
611
612	#if (!defined(__ARM_ARCH_6M__) \|\| __ARM_ARCH_6M__==0)
613
614	__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
615	{
616	return __LDREX((unsigned long *)ptr);
617	}
618
619	__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
620	{
621	return __STREX(value, (unsigned long *)ptr);
622	}
623	#endif
624
625
626	/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
627	#if (__CORTEX_M >= 0x03)
628
629	__IAR_FT uint32_t __RRX(uint32_t value)
630	{
631	uint32_t result;
632	__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
633	return(result);
634	}
635
636	__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
637	{
638	__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
639	}
640
641
642	#define __enable_fault_irq __enable_fiq
643	#define __disable_fault_irq __disable_fiq
644
645
646	#endif /* (__CORTEX_M >= 0x03) */
647
648	__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
649	{
650	return (op1 >> op2) \| (op1 << ((sizeof(op1)*8)-op2));
651	}
652
653	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
654	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
655
656	__IAR_FT uint32_t __get_MSPLIM(void)
657	{
658	uint32_t res;
659	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
660	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
661	// without main extensions, the non-secure MSPLIM is RAZ/WI
662	res = 0U;
663	#else
664	__asm volatile("MRS %0,MSPLIM" : "=r" (res));
665	#endif
666	return res;
667	}
668
669	__IAR_FT void __set_MSPLIM(uint32_t value)
670	{
671	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
672	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
673	// without main extensions, the non-secure MSPLIM is RAZ/WI
674	(void)value;
675	#else
676	__asm volatile("MSR MSPLIM,%0" :: "r" (value));
677	#endif
678	}
679
680	__IAR_FT uint32_t __get_PSPLIM(void)
681	{
682	uint32_t res;
683	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
684	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
685	// without main extensions, the non-secure PSPLIM is RAZ/WI
686	res = 0U;
687	#else
688	__asm volatile("MRS %0,PSPLIM" : "=r" (res));
689	#endif
690	return res;
691	}
692
693	__IAR_FT void __set_PSPLIM(uint32_t value)
694	{
695	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
696	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
697	// without main extensions, the non-secure PSPLIM is RAZ/WI
698	(void)value;
699	#else
700	__asm volatile("MSR PSPLIM,%0" :: "r" (value));
701	#endif
702	}
703
704	__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
705	{
706	uint32_t res;
707	__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
708	return res;
709	}
710
711	__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
712	{
713	__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
714	__iar_builtin_ISB();
715	}
716
717	__IAR_FT uint32_t __TZ_get_PSP_NS(void)
718	{
719	uint32_t res;
720	__asm volatile("MRS %0,PSP_NS" : "=r" (res));
721	return res;
722	}
723
724	__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
725	{
726	__asm volatile("MSR PSP_NS,%0" :: "r" (value));
727	}
728
729	__IAR_FT uint32_t __TZ_get_MSP_NS(void)
730	{
731	uint32_t res;
732	__asm volatile("MRS %0,MSP_NS" : "=r" (res));
733	return res;
734	}
735
736	__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
737	{
738	__asm volatile("MSR MSP_NS,%0" :: "r" (value));
739	}
740
741	__IAR_FT uint32_t __TZ_get_SP_NS(void)
742	{
743	uint32_t res;
744	__asm volatile("MRS %0,SP_NS" : "=r" (res));
745	return res;
746	}
747	__IAR_FT void __TZ_set_SP_NS(uint32_t value)
748	{
749	__asm volatile("MSR SP_NS,%0" :: "r" (value));
750	}
751
752	__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
753	{
754	uint32_t res;
755	__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
756	return res;
757	}
758
759	__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
760	{
761	__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
762	}
763
764	__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
765	{
766	uint32_t res;
767	__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
768	return res;
769	}
770
771	__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
772	{
773	__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
774	}
775
776	__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
777	{
778	uint32_t res;
779	__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
780	return res;
781	}
782
783	__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
784	{
785	__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
786	}
787
788	__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
789	{
790	uint32_t res;
791	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
792	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
793	// without main extensions, the non-secure PSPLIM is RAZ/WI
794	res = 0U;
795	#else
796	__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
797	#endif
798	return res;
799	}
800
801	__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
802	{
803	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
804	(!defined (__ARM_FEATURE_CMSE ) \|\| (__ARM_FEATURE_CMSE < 3)))
805	// without main extensions, the non-secure PSPLIM is RAZ/WI
806	(void)value;
807	#else
808	__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
809	#endif
810	}
811
812	__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
813	{
814	uint32_t res;
815	__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
816	return res;
817	}
818
819	__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
820	{
821	__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
822	}
823
824	#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
825
826	#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
827
828	#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
829
830	#if __IAR_M0_FAMILY
831	__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
832	{
833	if ((sat >= 1U) && (sat <= 32U))
834	{
835	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
836	const int32_t min = -1 - max ;
837	if (val > max)
838	{
839	return max;
840	}
841	else if (val < min)
842	{
843	return min;
844	}
845	}
846	return val;
847	}
848
849	__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
850	{
851	if (sat <= 31U)
852	{
853	const uint32_t max = ((1U << sat) - 1U);
854	if (val > (int32_t)max)
855	{
856	return max;
857	}
858	else if (val < 0)
859	{
860	return 0U;
861	}
862	}
863	return (uint32_t)val;
864	}
865	#endif
866
867	#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
868
869	__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
870	{
871	uint32_t res;
872	__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
873	return ((uint8_t)res);
874	}
875
876	__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
877	{
878	uint32_t res;
879	__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
880	return ((uint16_t)res);
881	}
882
883	__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
884	{
885	uint32_t res;
886	__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
887	return res;
888	}
889
890	__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
891	{
892	__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
893	}
894
895	__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
896	{
897	__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
898	}
899
900	__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
901	{
902	__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
903	}
904
905	#endif /* (__CORTEX_M >= 0x03) */
906
907	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
908	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
909
910
911	__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
912	{
913	uint32_t res;
914	__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
915	return ((uint8_t)res);
916	}
917
918	__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
919	{
920	uint32_t res;
921	__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
922	return ((uint16_t)res);
923	}
924
925	__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
926	{
927	uint32_t res;
928	__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
929	return res;
930	}
931
932	__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
933	{
934	__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
935	}
936
937	__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
938	{
939	__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
940	}
941
942	__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
943	{
944	__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
945	}
946
947	__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
948	{
949	uint32_t res;
950	__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
951	return ((uint8_t)res);
952	}
953
954	__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
955	{
956	uint32_t res;
957	__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
958	return ((uint16_t)res);
959	}
960
961	__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
962	{
963	uint32_t res;
964	__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
965	return res;
966	}
967
968	__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
969	{
970	uint32_t res;
971	__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
972	return res;
973	}
974
975	__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
976	{
977	uint32_t res;
978	__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
979	return res;
980	}
981
982	__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
983	{
984	uint32_t res;
985	__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
986	return res;
987	}
988
989	#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
990
991	#undef __IAR_FT
992	#undef __IAR_M0_FAMILY
993	#undef __ICCARM_V8
994
995	#pragma diag_default=Pe940
996	#pragma diag_default=Pe177
997
998	#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
999
1000	#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1001
1002	#endif /* __CMSIS_ICCARM_H__ */

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source: trunk/firmware_cube/Drivers/CMSIS/Include/cmsis_iccarm.h @ 9

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