Changeset 74 for ctrl/firmware/Main/CubeMX
- Timestamp:
- Jan 29, 2025, 1:36:43 PM (3 months ago)
- Location:
- ctrl/firmware/Main/CubeMX
- Files:
-
- 22 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
ctrl/firmware/Main/CubeMX/Core/Src/freertos.c
r73 r74 27 27 /* USER CODE BEGIN Includes */ 28 28 29 #include "stdio.h" 30 29 31 #include "keys_task.h" 30 32 … … 40 42 /* USER CODE BEGIN PD */ 41 43 44 #define KEYS_TASK_STACK_DEPTH_WORDS (128U) 45 42 46 /* USER CODE END PD */ 43 47 … … 50 54 /* USER CODE BEGIN Variables */ 51 55 52 const uint16_t KEYS_TASK_STACK_DEPTH_WORDS = 128U; 56 static StackType_t keysTaskStackBuffer[KEYS_TASK_STACK_DEPTH_WORDS] __attribute__((section(".DTCM_RAM"))); 57 static StaticTask_t keysTaskBuffer; 58 static const char* const keysTaskName = "ScanKeysTask"; 53 59 54 60 /* USER CODE END Variables */ 55 61 /* Definitions for mainTask */ 56 62 osThreadId_t mainTaskHandle; 57 uint32_t mainTaskBuffer[ 128];63 uint32_t mainTaskBuffer[ 512 ]; 58 64 osStaticThreadDef_t mainTaskControlBlock; 59 65 const osThreadAttr_t mainTask_attributes = { … … 73 79 void mainTaskStart(void *argument); 74 80 75 //void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */81 void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ 76 82 77 83 /* Hook prototypes */ … … 132 138 /* add threads, ... */ 133 139 134 BaseType_t r = xTaskCreate(keysTaskStart, "ScanKeysTask", KEYS_TASK_STACK_DEPTH_WORDS, NULL, 0, NULL); 140 TaskHandle_t r = xTaskCreateStatic(keysTaskStart, keysTaskName, KEYS_TASK_STACK_DEPTH_WORDS, NULL, 25, keysTaskStackBuffer, &keysTaskBuffer); 141 if (r == NULL) printf("Cannot create %s!\n", keysTaskName); 135 142 136 143 /* USER CODE END RTOS_THREADS */ -
ctrl/firmware/Main/CubeMX/Core/Src/main.c
r73 r74 21 21 #include "cmsis_os.h" 22 22 #include "dma.h" 23 #include "fatfs.h" 23 24 #include "memorymap.h" 24 25 #include "rtc.h" … … 123 124 MX_TIM3_Init(); 124 125 MX_TIM8_Init(); 126 MX_FATFS_Init(); 125 127 /* USER CODE BEGIN 2 */ 126 128 -
ctrl/firmware/Main/CubeMX/Core/Src/sdmmc.c
r72 r74 47 47 hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_ENABLE; 48 48 hsd1.Init.ClockDiv = 0; 49 if (HAL_SD_Init(&hsd1) != HAL_OK)50 {51 Error_Handler();52 }53 49 /* USER CODE BEGIN SDMMC1_Init 2 */ 54 50 … … 106 102 107 103 /* SDMMC1 interrupt Init */ 108 HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 0);104 HAL_NVIC_SetPriority(SDMMC1_IRQn, 15, 0); 109 105 HAL_NVIC_EnableIRQ(SDMMC1_IRQn); 110 106 /* USER CODE BEGIN SDMMC1_MspInit 1 */ -
ctrl/firmware/Main/CubeMX/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
r73 r74 62 62 extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; 63 63 #else 64 static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] ;64 static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] __attribute__((section(".DTCM_RAM"))); 65 65 #endif /* configAPPLICATION_ALLOCATED_HEAP */ 66 66 -
ctrl/firmware/Main/CubeMX/charger.ioc
r73 r74 1 1 #MicroXplorer Configuration settings - do not modify 2 CAD.formats= 3 CAD.pinconfig= 2 CAD.formats=[] 3 CAD.pinconfig=Dual 4 4 CAD.provider= 5 5 CORTEX_M7.CPU_DCache=Enabled … … 66 66 Dma.USART3_TX.2.SyncRequestNumber=1 67 67 Dma.USART3_TX.2.SyncSignalID=NONE 68 FATFS.BSP.number=1 69 FATFS.IPParameters=_USE_FIND,_USE_EXPAND,_USE_LABEL,_USE_LFN,_LFN_UNICODE,_MULTI_PARTITION,_FS_EXFAT,_USE_MUTEX,_FS_REENTRANT,_FS_NORTC,_NORTC_YEAR,_NORTC_MDAY,_NORTC_MON 70 FATFS._FS_EXFAT=1 71 FATFS._FS_NORTC=1 72 FATFS._FS_REENTRANT=0 73 FATFS._LFN_UNICODE=1 74 FATFS._MULTI_PARTITION=0 75 FATFS._NORTC_MDAY=1 76 FATFS._NORTC_MON=1 77 FATFS._NORTC_YEAR=2025 78 FATFS._USE_EXPAND=1 79 FATFS._USE_FIND=1 80 FATFS._USE_LABEL=1 81 FATFS._USE_LFN=2 82 FATFS._USE_MUTEX=1 83 FATFS0.BSP.STBoard=false 84 FATFS0.BSP.api=Unknown 85 FATFS0.BSP.component= 86 FATFS0.BSP.condition= 87 FATFS0.BSP.instance=PA8 88 FATFS0.BSP.ip=GPIO 89 FATFS0.BSP.mode=Input 90 FATFS0.BSP.name=Detect_SDIO 91 FATFS0.BSP.semaphore= 92 FATFS0.BSP.solution=PA8 68 93 FREERTOS.FootprintOK=true 69 94 FREERTOS.INCLUDE_uxTaskGetStackHighWaterMark2=1 … … 79 104 GPIO.groupedBy=Group By Peripherals 80 105 KeepUserPlacement=false 81 MMTAppRegionsCount=0 106 MMTAppReg1.MEMORYMAP.AppRegionName=DTCMRAM 107 MMTAppReg1.MEMORYMAP.Cacheability=WBRAWA 108 MMTAppReg1.MEMORYMAP.ContextName=Cortex-M7NS 109 MMTAppReg1.MEMORYMAP.CoreName=Arm Cortex-M7 110 MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability 111 MMTAppReg1.MEMORYMAP.Name=DTCMRAM 112 MMTAppReg1.MEMORYMAP.Size=131072 113 MMTAppReg1.MEMORYMAP.StartAddress=0x20000000 114 MMTAppReg2.MEMORYMAP.AppRegionName=RAM 115 MMTAppReg2.MEMORYMAP.Cacheability=WBRAWA 116 MMTAppReg2.MEMORYMAP.ContextName=Cortex-M7NS 117 MMTAppReg2.MEMORYMAP.CoreName=Arm Cortex-M7 118 MMTAppReg2.MEMORYMAP.DefaultDataRegion=true 119 MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability,DefaultDataRegion 120 MMTAppReg2.MEMORYMAP.Name=RAM 121 MMTAppReg2.MEMORYMAP.Size=131072 122 MMTAppReg2.MEMORYMAP.StartAddress=0x24000000 123 MMTAppReg3.MEMORYMAP.AppRegionName=RAM_D2 124 MMTAppReg3.MEMORYMAP.Cacheability=WBRAWA 125 MMTAppReg3.MEMORYMAP.ContextName=Cortex-M7NS 126 MMTAppReg3.MEMORYMAP.CoreName=Arm Cortex-M7 127 MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability 128 MMTAppReg3.MEMORYMAP.Name=RAM_D2 129 MMTAppReg3.MEMORYMAP.Size=32768 130 MMTAppReg3.MEMORYMAP.StartAddress=0x30000000 131 MMTAppReg4.MEMORYMAP.AppRegionName=RAM_D3 132 MMTAppReg4.MEMORYMAP.Cacheability=WBRAWA 133 MMTAppReg4.MEMORYMAP.ContextName=Cortex-M7NS 134 MMTAppReg4.MEMORYMAP.CoreName=Arm Cortex-M7 135 MMTAppReg4.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability 136 MMTAppReg4.MEMORYMAP.Name=RAM_D3 137 MMTAppReg4.MEMORYMAP.Size=16384 138 MMTAppReg4.MEMORYMAP.StartAddress=0x38000000 139 MMTAppReg5.MEMORYMAP.AppRegionName=ITCMRAM 140 MMTAppReg5.MEMORYMAP.Cacheability=WTRA 141 MMTAppReg5.MEMORYMAP.ContextName=Cortex-M7NS 142 MMTAppReg5.MEMORYMAP.CoreName=Arm Cortex-M7 143 MMTAppReg5.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability 144 MMTAppReg5.MEMORYMAP.Name=ITCMRAM 145 MMTAppReg5.MEMORYMAP.Size=65536 146 MMTAppReg5.MEMORYMAP.StartAddress=0x00000000 147 MMTAppReg6.MEMORYMAP.AP=RO_priv_only 148 MMTAppReg6.MEMORYMAP.AppRegionName=FLASH 149 MMTAppReg6.MEMORYMAP.Cacheability=WTRA 150 MMTAppReg6.MEMORYMAP.ContextName=Cortex-M7NS 151 MMTAppReg6.MEMORYMAP.CoreName=Arm Cortex-M7 152 MMTAppReg6.MEMORYMAP.DefaultCodeRegion=true 153 MMTAppReg6.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion,ISRRegion,RootBootRegion 154 MMTAppReg6.MEMORYMAP.ISRRegion=true 155 MMTAppReg6.MEMORYMAP.MemType=ROM 156 MMTAppReg6.MEMORYMAP.Name=FLASH 157 MMTAppReg6.MEMORYMAP.RootBootRegion=true 158 MMTAppReg6.MEMORYMAP.Size=524288 159 MMTAppReg6.MEMORYMAP.StartAddress=0x08000000 160 MMTAppRegionsCount=6 82 161 MMTConfigApplied=false 83 162 Mcu.CPN=STM32H723ZET6 … … 85 164 Mcu.IP0=CORTEX_M7 86 165 Mcu.IP1=DEBUG 87 Mcu.IP10=SYS 88 Mcu.IP11=TIM3 89 Mcu.IP12=TIM8 90 Mcu.IP13=USART3 166 Mcu.IP10=SPI4 167 Mcu.IP11=SYS 168 Mcu.IP12=TIM3 169 Mcu.IP13=TIM8 170 Mcu.IP14=USART3 91 171 Mcu.IP2=DMA 92 Mcu.IP3=F REERTOS93 Mcu.IP4= MEMORYMAP94 Mcu.IP5= NVIC95 Mcu.IP6= RCC96 Mcu.IP7=R TC97 Mcu.IP8= SDMMC198 Mcu.IP9=S PI499 Mcu.IPNb=1 4172 Mcu.IP3=FATFS 173 Mcu.IP4=FREERTOS 174 Mcu.IP5=MEMORYMAP 175 Mcu.IP6=NVIC 176 Mcu.IP7=RCC 177 Mcu.IP8=RTC 178 Mcu.IP9=SDMMC1 179 Mcu.IPNb=15 100 180 Mcu.Name=STM32H723ZETx 101 181 Mcu.Package=LQFP144 … … 132 212 Mcu.Pin36=PG13 133 213 Mcu.Pin37=PG15 134 Mcu.Pin38=VP_F REERTOS_VS_CMSIS_V2135 Mcu.Pin39=VP_ RTC_VS_RTC_Activate214 Mcu.Pin38=VP_FATFS_VS_SDIO 215 Mcu.Pin39=VP_FREERTOS_VS_CMSIS_V2 136 216 Mcu.Pin4=PH1-OSC_OUT 137 Mcu.Pin40=VP_SYS_VS_tim7 138 Mcu.Pin41=VP_TIM3_VS_ClockSourceINT 139 Mcu.Pin42=VP_TIM8_VS_ControllerModeReset 140 Mcu.Pin43=VP_TIM8_VS_ClockSourceINT 141 Mcu.Pin44=VP_MEMORYMAP_VS_MEMORYMAP 217 Mcu.Pin40=VP_RTC_VS_RTC_Activate 218 Mcu.Pin41=VP_RTC_VS_RTC_Calendar 219 Mcu.Pin42=VP_SYS_VS_tim7 220 Mcu.Pin43=VP_TIM3_VS_ClockSourceINT 221 Mcu.Pin44=VP_TIM8_VS_ControllerModeReset 222 Mcu.Pin45=VP_TIM8_VS_ClockSourceINT 223 Mcu.Pin46=VP_MEMORYMAP_VS_MEMORYMAP 142 224 Mcu.Pin5=PF15 143 225 Mcu.Pin6=PG0 … … 145 227 Mcu.Pin8=PE7 146 228 Mcu.Pin9=PE11 147 Mcu.PinsNb=4 5229 Mcu.PinsNb=47 148 230 Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-H7.3.3.0 149 231 Mcu.ThirdPartyNb=1 … … 337 419 ProjectManager.UAScriptBeforePath= 338 420 ProjectManager.UnderRoot=true 339 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_SPI4_Init-SPI4-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_TIM8_Init-TIM8-false-HAL-true, 0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true421 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_SPI4_Init-SPI4-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_TIM8_Init-TIM8-false-HAL-true,10-MX_FATFS_Init-FATFS-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true 340 422 RCC.ADCFreq_Value=166666666.66666666 341 423 RCC.AHB12Freq_Value=100000000 … … 474 556 USART3.SwapParam=ADVFEATURE_SWAP_ENABLE 475 557 USART3.VirtualMode-Asynchronous=VM_ASYNC 558 VP_FATFS_VS_SDIO.Mode=SDIO 559 VP_FATFS_VS_SDIO.Signal=FATFS_VS_SDIO 476 560 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 477 561 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 … … 480 564 VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled 481 565 VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate 566 VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar 567 VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar 482 568 VP_SYS_VS_tim7.Mode=TIM7 483 569 VP_SYS_VS_tim7.Signal=SYS_VS_tim7
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