Changeset 79 for ctrl/firmware/Main/CubeMX/Core
- Timestamp:
- Feb 4, 2025, 1:58:46 PM (3 months ago)
- Location:
- ctrl/firmware/Main/CubeMX/Core
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h
r77 r79 56 56 void DMA1_Stream1_IRQHandler(void); 57 57 void DMA1_Stream2_IRQHandler(void); 58 void DMA1_Stream3_IRQHandler(void); 59 void DMA1_Stream4_IRQHandler(void); 58 60 void EXTI9_5_IRQHandler(void); 59 61 void TIM3_IRQHandler(void); -
ctrl/firmware/Main/CubeMX/Core/Src/dma.c
r72 r79 53 53 HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 54 54 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 55 /* DMA1_Stream3_IRQn interrupt configuration */ 56 HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); 57 HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); 58 /* DMA1_Stream4_IRQn interrupt configuration */ 59 HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); 60 HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 55 61 56 62 } -
ctrl/firmware/Main/CubeMX/Core/Src/freertos.c
r74 r79 30 30 31 31 #include "keys_task.h" 32 #include "eth_task.h" 32 33 33 34 /* USER CODE END Includes */ … … 43 44 44 45 #define KEYS_TASK_STACK_DEPTH_WORDS (128U) 46 #define ETH_TASK_STACK_DEPTH_WORDS (2048U) 45 47 46 48 /* USER CODE END PD */ … … 55 57 56 58 static StackType_t keysTaskStackBuffer[KEYS_TASK_STACK_DEPTH_WORDS] __attribute__((section(".DTCM_RAM"))); 59 static StackType_t ethTaskStackBuffer[ETH_TASK_STACK_DEPTH_WORDS] __attribute__((section(".DTCM_RAM"))); 57 60 static StaticTask_t keysTaskBuffer; 61 static StaticTask_t ethTaskBuffer; 58 62 static const char* const keysTaskName = "ScanKeysTask"; 63 static const char* const ethTaskName = "EthTask"; 59 64 60 65 /* USER CODE END Variables */ … … 141 146 if (r == NULL) printf("Cannot create %s!\n", keysTaskName); 142 147 148 r = xTaskCreateStatic(ethTaskStart, ethTaskName, ETH_TASK_STACK_DEPTH_WORDS, NULL, 25, ethTaskStackBuffer, ðTaskBuffer); 149 if (r == NULL) printf("Cannot create %s!\n", ethTaskName); 150 143 151 /* USER CODE END RTOS_THREADS */ 144 152 -
ctrl/firmware/Main/CubeMX/Core/Src/spi.c
r78 r79 27 27 SPI_HandleTypeDef hspi2; 28 28 SPI_HandleTypeDef hspi4; 29 DMA_HandleTypeDef hdma_spi2_rx; 30 DMA_HandleTypeDef hdma_spi2_tx; 29 31 DMA_HandleTypeDef hdma_spi4_tx; 30 32 … … 44 46 hspi2.Init.Direction = SPI_DIRECTION_2LINES; 45 47 hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 46 hspi2.Init.CLKPolarity = SPI_POLARITY_ HIGH;47 hspi2.Init.CLKPhase = SPI_PHASE_ 2EDGE;48 hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 49 hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 48 50 hspi2.Init.NSS = SPI_NSS_SOFT; 49 51 hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; … … 158 160 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 159 161 162 /* SPI2 DMA Init */ 163 /* SPI2_RX Init */ 164 hdma_spi2_rx.Instance = DMA1_Stream3; 165 hdma_spi2_rx.Init.Request = DMA_REQUEST_SPI2_RX; 166 hdma_spi2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 167 hdma_spi2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 168 hdma_spi2_rx.Init.MemInc = DMA_MINC_ENABLE; 169 hdma_spi2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 170 hdma_spi2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 171 hdma_spi2_rx.Init.Mode = DMA_NORMAL; 172 hdma_spi2_rx.Init.Priority = DMA_PRIORITY_HIGH; 173 hdma_spi2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 174 if (HAL_DMA_Init(&hdma_spi2_rx) != HAL_OK) 175 { 176 Error_Handler(); 177 } 178 179 __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi2_rx); 180 181 /* SPI2_TX Init */ 182 hdma_spi2_tx.Instance = DMA1_Stream4; 183 hdma_spi2_tx.Init.Request = DMA_REQUEST_SPI2_TX; 184 hdma_spi2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 185 hdma_spi2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 186 hdma_spi2_tx.Init.MemInc = DMA_MINC_ENABLE; 187 hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 188 hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 189 hdma_spi2_tx.Init.Mode = DMA_NORMAL; 190 hdma_spi2_tx.Init.Priority = DMA_PRIORITY_HIGH; 191 hdma_spi2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 192 if (HAL_DMA_Init(&hdma_spi2_tx) != HAL_OK) 193 { 194 Error_Handler(); 195 } 196 197 __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi2_tx); 198 160 199 /* SPI2 interrupt Init */ 161 200 HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0); … … 242 281 HAL_GPIO_DeInit(GPIOB, ETH_SPI_SCK_Pin|ETH_SPI_MISO_Pin|ETH_SPI_MOSI_Pin); 243 282 283 /* SPI2 DMA DeInit */ 284 HAL_DMA_DeInit(spiHandle->hdmarx); 285 HAL_DMA_DeInit(spiHandle->hdmatx); 286 244 287 /* SPI2 interrupt Deinit */ 245 288 HAL_NVIC_DisableIRQ(SPI2_IRQn); -
ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c
r77 r79 61 61 /* External variables --------------------------------------------------------*/ 62 62 extern SD_HandleTypeDef hsd1; 63 extern DMA_HandleTypeDef hdma_spi2_rx; 64 extern DMA_HandleTypeDef hdma_spi2_tx; 63 65 extern DMA_HandleTypeDef hdma_spi4_tx; 64 66 extern SPI_HandleTypeDef hspi2; … … 216 218 217 219 /** 220 * @brief This function handles DMA1 stream3 global interrupt. 221 */ 222 void DMA1_Stream3_IRQHandler(void) 223 { 224 /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ 225 226 /* USER CODE END DMA1_Stream3_IRQn 0 */ 227 HAL_DMA_IRQHandler(&hdma_spi2_rx); 228 /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ 229 230 /* USER CODE END DMA1_Stream3_IRQn 1 */ 231 } 232 233 /** 234 * @brief This function handles DMA1 stream4 global interrupt. 235 */ 236 void DMA1_Stream4_IRQHandler(void) 237 { 238 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ 239 240 /* USER CODE END DMA1_Stream4_IRQn 0 */ 241 HAL_DMA_IRQHandler(&hdma_spi2_tx); 242 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ 243 244 /* USER CODE END DMA1_Stream4_IRQn 1 */ 245 } 246 247 /** 218 248 * @brief This function handles EXTI line[9:5] interrupts. 219 249 */
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