Changeset 79
- Timestamp:
- Feb 4, 2025, 1:58:46 PM (3 months ago)
- Location:
- ctrl/firmware/Main
- Files:
-
- 13 added
- 8 edited
- 2 moved
Legend:
- Unmodified
- Added
- Removed
-
ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h
r77 r79 56 56 void DMA1_Stream1_IRQHandler(void); 57 57 void DMA1_Stream2_IRQHandler(void); 58 void DMA1_Stream3_IRQHandler(void); 59 void DMA1_Stream4_IRQHandler(void); 58 60 void EXTI9_5_IRQHandler(void); 59 61 void TIM3_IRQHandler(void); -
ctrl/firmware/Main/CubeMX/Core/Src/dma.c
r72 r79 53 53 HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 54 54 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 55 /* DMA1_Stream3_IRQn interrupt configuration */ 56 HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); 57 HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); 58 /* DMA1_Stream4_IRQn interrupt configuration */ 59 HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); 60 HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); 55 61 56 62 } -
ctrl/firmware/Main/CubeMX/Core/Src/freertos.c
r74 r79 30 30 31 31 #include "keys_task.h" 32 #include "eth_task.h" 32 33 33 34 /* USER CODE END Includes */ … … 43 44 44 45 #define KEYS_TASK_STACK_DEPTH_WORDS (128U) 46 #define ETH_TASK_STACK_DEPTH_WORDS (2048U) 45 47 46 48 /* USER CODE END PD */ … … 55 57 56 58 static StackType_t keysTaskStackBuffer[KEYS_TASK_STACK_DEPTH_WORDS] __attribute__((section(".DTCM_RAM"))); 59 static StackType_t ethTaskStackBuffer[ETH_TASK_STACK_DEPTH_WORDS] __attribute__((section(".DTCM_RAM"))); 57 60 static StaticTask_t keysTaskBuffer; 61 static StaticTask_t ethTaskBuffer; 58 62 static const char* const keysTaskName = "ScanKeysTask"; 63 static const char* const ethTaskName = "EthTask"; 59 64 60 65 /* USER CODE END Variables */ … … 141 146 if (r == NULL) printf("Cannot create %s!\n", keysTaskName); 142 147 148 r = xTaskCreateStatic(ethTaskStart, ethTaskName, ETH_TASK_STACK_DEPTH_WORDS, NULL, 25, ethTaskStackBuffer, ðTaskBuffer); 149 if (r == NULL) printf("Cannot create %s!\n", ethTaskName); 150 143 151 /* USER CODE END RTOS_THREADS */ 144 152 -
ctrl/firmware/Main/CubeMX/Core/Src/spi.c
r78 r79 27 27 SPI_HandleTypeDef hspi2; 28 28 SPI_HandleTypeDef hspi4; 29 DMA_HandleTypeDef hdma_spi2_rx; 30 DMA_HandleTypeDef hdma_spi2_tx; 29 31 DMA_HandleTypeDef hdma_spi4_tx; 30 32 … … 44 46 hspi2.Init.Direction = SPI_DIRECTION_2LINES; 45 47 hspi2.Init.DataSize = SPI_DATASIZE_8BIT; 46 hspi2.Init.CLKPolarity = SPI_POLARITY_ HIGH;47 hspi2.Init.CLKPhase = SPI_PHASE_ 2EDGE;48 hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 49 hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 48 50 hspi2.Init.NSS = SPI_NSS_SOFT; 49 51 hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; … … 158 160 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 159 161 162 /* SPI2 DMA Init */ 163 /* SPI2_RX Init */ 164 hdma_spi2_rx.Instance = DMA1_Stream3; 165 hdma_spi2_rx.Init.Request = DMA_REQUEST_SPI2_RX; 166 hdma_spi2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 167 hdma_spi2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 168 hdma_spi2_rx.Init.MemInc = DMA_MINC_ENABLE; 169 hdma_spi2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 170 hdma_spi2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 171 hdma_spi2_rx.Init.Mode = DMA_NORMAL; 172 hdma_spi2_rx.Init.Priority = DMA_PRIORITY_HIGH; 173 hdma_spi2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 174 if (HAL_DMA_Init(&hdma_spi2_rx) != HAL_OK) 175 { 176 Error_Handler(); 177 } 178 179 __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi2_rx); 180 181 /* SPI2_TX Init */ 182 hdma_spi2_tx.Instance = DMA1_Stream4; 183 hdma_spi2_tx.Init.Request = DMA_REQUEST_SPI2_TX; 184 hdma_spi2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 185 hdma_spi2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 186 hdma_spi2_tx.Init.MemInc = DMA_MINC_ENABLE; 187 hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 188 hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 189 hdma_spi2_tx.Init.Mode = DMA_NORMAL; 190 hdma_spi2_tx.Init.Priority = DMA_PRIORITY_HIGH; 191 hdma_spi2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 192 if (HAL_DMA_Init(&hdma_spi2_tx) != HAL_OK) 193 { 194 Error_Handler(); 195 } 196 197 __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi2_tx); 198 160 199 /* SPI2 interrupt Init */ 161 200 HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0); … … 242 281 HAL_GPIO_DeInit(GPIOB, ETH_SPI_SCK_Pin|ETH_SPI_MISO_Pin|ETH_SPI_MOSI_Pin); 243 282 283 /* SPI2 DMA DeInit */ 284 HAL_DMA_DeInit(spiHandle->hdmarx); 285 HAL_DMA_DeInit(spiHandle->hdmatx); 286 244 287 /* SPI2 interrupt Deinit */ 245 288 HAL_NVIC_DisableIRQ(SPI2_IRQn); -
ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c
r77 r79 61 61 /* External variables --------------------------------------------------------*/ 62 62 extern SD_HandleTypeDef hsd1; 63 extern DMA_HandleTypeDef hdma_spi2_rx; 64 extern DMA_HandleTypeDef hdma_spi2_tx; 63 65 extern DMA_HandleTypeDef hdma_spi4_tx; 64 66 extern SPI_HandleTypeDef hspi2; … … 216 218 217 219 /** 220 * @brief This function handles DMA1 stream3 global interrupt. 221 */ 222 void DMA1_Stream3_IRQHandler(void) 223 { 224 /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ 225 226 /* USER CODE END DMA1_Stream3_IRQn 0 */ 227 HAL_DMA_IRQHandler(&hdma_spi2_rx); 228 /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ 229 230 /* USER CODE END DMA1_Stream3_IRQn 1 */ 231 } 232 233 /** 234 * @brief This function handles DMA1 stream4 global interrupt. 235 */ 236 void DMA1_Stream4_IRQHandler(void) 237 { 238 /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ 239 240 /* USER CODE END DMA1_Stream4_IRQn 0 */ 241 HAL_DMA_IRQHandler(&hdma_spi2_tx); 242 /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ 243 244 /* USER CODE END DMA1_Stream4_IRQn 1 */ 245 } 246 247 /** 218 248 * @brief This function handles EXTI line[9:5] interrupts. 219 249 */ -
ctrl/firmware/Main/CubeMX/charger.ioc
r77 r79 11 11 Dma.Request1=USART3_RX 12 12 Dma.Request2=USART3_TX 13 Dma.RequestsNb=3 13 Dma.Request3=SPI2_RX 14 Dma.Request4=SPI2_TX 15 Dma.RequestsNb=5 16 Dma.SPI2_RX.3.Direction=DMA_PERIPH_TO_MEMORY 17 Dma.SPI2_RX.3.EventEnable=DISABLE 18 Dma.SPI2_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE 19 Dma.SPI2_RX.3.Instance=DMA1_Stream3 20 Dma.SPI2_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE 21 Dma.SPI2_RX.3.MemInc=DMA_MINC_ENABLE 22 Dma.SPI2_RX.3.Mode=DMA_NORMAL 23 Dma.SPI2_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE 24 Dma.SPI2_RX.3.PeriphInc=DMA_PINC_DISABLE 25 Dma.SPI2_RX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING 26 Dma.SPI2_RX.3.Priority=DMA_PRIORITY_HIGH 27 Dma.SPI2_RX.3.RequestNumber=1 28 Dma.SPI2_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber 29 Dma.SPI2_RX.3.SignalID=NONE 30 Dma.SPI2_RX.3.SyncEnable=DISABLE 31 Dma.SPI2_RX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT 32 Dma.SPI2_RX.3.SyncRequestNumber=1 33 Dma.SPI2_RX.3.SyncSignalID=NONE 34 Dma.SPI2_TX.4.Direction=DMA_MEMORY_TO_PERIPH 35 Dma.SPI2_TX.4.EventEnable=DISABLE 36 Dma.SPI2_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE 37 Dma.SPI2_TX.4.Instance=DMA1_Stream4 38 Dma.SPI2_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE 39 Dma.SPI2_TX.4.MemInc=DMA_MINC_ENABLE 40 Dma.SPI2_TX.4.Mode=DMA_NORMAL 41 Dma.SPI2_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE 42 Dma.SPI2_TX.4.PeriphInc=DMA_PINC_DISABLE 43 Dma.SPI2_TX.4.Polarity=HAL_DMAMUX_REQ_GEN_RISING 44 Dma.SPI2_TX.4.Priority=DMA_PRIORITY_HIGH 45 Dma.SPI2_TX.4.RequestNumber=1 46 Dma.SPI2_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber 47 Dma.SPI2_TX.4.SignalID=NONE 48 Dma.SPI2_TX.4.SyncEnable=DISABLE 49 Dma.SPI2_TX.4.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT 50 Dma.SPI2_TX.4.SyncRequestNumber=1 51 Dma.SPI2_TX.4.SyncSignalID=NONE 14 52 Dma.SPI4_TX.0.Direction=DMA_MEMORY_TO_PERIPH 15 53 Dma.SPI4_TX.0.EventEnable=DISABLE … … 248 286 NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 249 287 NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 288 NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 289 NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true 250 290 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false 251 291 NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true -
ctrl/firmware/Main/SES/Core/Inc/eth_task.h
r78 r79 1 1 #ifndef __ETH_THREAD_H 2 2 #define __ETH_THREAD_H 3 4 #include "tx_api.h"5 3 6 4 #ifdef __cplusplus … … 9 7 #endif 10 8 11 VOID ethThread(ULONG initial_input);9 void ethTaskStart(void* argument); 12 10 13 11 #ifdef __cplusplus -
ctrl/firmware/Main/SES/Core/Src/eth_task.cpp
r78 r79 2 2 #include <cstdint> 3 3 4 #include "main.h" 5 #include "FreeRTOS.h" 6 #include "task.h" 4 7 5 #include "eth_thread.h" 8 #include "eth_task.h" 9 10 #include "loopback.h" 11 #include "wizchip_conf.h" 12 #include "dhcp.h" 6 13 7 14 8 VOID ethThread(ULONG initial_input) 15 static constexpr unsigned ETH_MAX_BUF_SIZE = 2048U; 16 static constexpr unsigned SOCKET_DHCP = 1; 17 18 static constexpr uint16_t delay_ms = 500U; 19 20 21 static uint8_t dhcp_buffer[ETH_MAX_BUF_SIZE]; 22 23 wiz_NetInfo gWIZNETINFO = { 24 .mac = {0x00, 0x08, 0xdc, 0x6f, 0x00, 0x8a}, 25 .ip = {192, 168, 11, 109}, 26 .sn = {255, 255, 255, 0}, 27 .gw = {192, 168, 11, 1}, 28 .dns = {8, 8, 8, 8}, 29 .dhcp = NETINFO_DHCP 30 }; 31 32 static void ip_assigned(void); 33 static void ip_updated(void); 34 static void ip_conflict(void); 35 static void wizchip_initialize(void); 36 static void wizchip_reset(void); 37 static void wizchip_check(void); 38 static void wizchip_dhcp_init(void); 39 40 //------------------------------------------------------------------------------ 41 42 void ethTaskStart(void* argument) 9 43 { 10 (void) initial_input;44 (void)argument; 11 45 46 wizchip_initialize(); 47 48 if (gWIZNETINFO.dhcp == NETINFO_DHCP) // DHCP 49 { 50 wizchip_dhcp_init(); 51 52 while (DHCP_run() != DHCP_IP_LEASED) 53 wiz_delay_ms(1000); 54 } 55 else // static 56 { 57 ctlnetwork(CN_SET_NETINFO, &gWIZNETINFO); 58 printf("\r\n----------STATIC Net Information--------------\r\n"); 59 //print_network_information(); 60 } 12 61 13 62 while (1) 14 63 { 15 tx_thread_sleep(1000U); 64 if (gWIZNETINFO.dhcp == NETINFO_DHCP) DHCP_run(); 65 66 loopback_tcps(2, dhcp_buffer, 5000U); 67 68 vTaskDelay(delay_ms); 16 69 } 17 70 } 71 72 //------------------------------------------------------------------------------ 73 74 void wizchip_reset(void) 75 { 76 HAL_GPIO_WritePin(ETH_SPI_PWR_GPIO_Port, ETH_SPI_PWR_Pin, GPIO_PIN_RESET); 77 vTaskDelay(pdMS_TO_TICKS(100U)); 78 HAL_GPIO_WritePin(ETH_SPI_RST_GPIO_Port, ETH_SPI_RST_Pin, GPIO_PIN_SET); 79 vTaskDelay(pdMS_TO_TICKS(65U)); // Min 60.3ms 80 } 81 82 //------------------------------------------------------------------------------ 83 84 void wizchip_initialize(void) 85 { 86 uint8_t W5100S_AdrSet[2][4]= {{2,2,2,2},{2,2,2,2}}; 87 uint8_t tmp1, tmp2; 88 intr_kind temp= IK_DEST_UNREACH; 89 90 wizchip_reset(); 91 92 if (ctlwizchip(CW_INIT_WIZCHIP, (void*)W5100S_AdrSet) == -1) 93 printf(">>>>W5100s memory initialization failed\r\n"); 94 95 if(ctlwizchip(CW_SET_INTRMASK,&temp) == -1) 96 printf("W5100S interrupt\r\n"); 97 98 wizchip_check(); 99 100 while(1) 101 { 102 ctlwizchip(CW_GET_PHYLINK, &tmp1 ); 103 ctlwizchip(CW_GET_PHYLINK, &tmp2 ); 104 if (tmp1 == PHY_LINK_ON && tmp2 == PHY_LINK_ON) break; 105 } 106 } 107 108 //------------------------------------------------------------------------------ 109 110 static void ip_assigned(void) 111 { 112 printf("IP-address was assigned.\n"); 113 114 uint8_t ip[4]; 115 getIPfromDHCP(ip); 116 printf("IP-address: %u.%u.%u.%u\n", ip[0], ip[1], ip[2], ip[3]); 117 118 uint8_t nm[4]; 119 getSNfromDHCP(nm); 120 printf("Subnet mask: %u.%u.%u.%u\n", nm[0], nm[1], nm[2], nm[3]); 121 122 uint8_t gw[4]; 123 getGWfromDHCP(gw); 124 printf("Gateway address: %u.%u.%u.%u\n", gw[0], gw[1], gw[2], gw[3]); 125 126 uint8_t dns[4]; 127 getDNSfromDHCP(dns); 128 printf("DNS address: %u.%u.%u.%u\n", dns[0], dns[1], dns[2], dns[3]); 129 130 printf("Lease time: %u\n", getDHCPLeasetime()); 131 } 132 133 //------------------------------------------------------------------------------ 134 135 static void ip_updated(void) 136 { 137 printf("IP-address was updated.\n"); 138 } 139 140 //------------------------------------------------------------------------------ 141 142 static void ip_conflict(void) 143 { 144 printf("IP-address conflict!.\n"); 145 } 146 147 //------------------------------------------------------------------------------ 148 149 void wizchip_check(void) 150 { 151 // Read version register 152 if (getVER() != 0x51) // W5100S 153 { 154 printf(" ACCESS ERR : VERSIONR != 0x51, read value = 0x%02x\n", getVER()); 155 while (1); 156 } 157 } 158 159 //------------------------------------------------------------------------------ 160 161 void wizchip_dhcp_init(void) 162 { 163 DHCP_init(SOCKET_DHCP, dhcp_buffer); 164 reg_dhcp_cbfunc(ip_assigned, ip_updated, ip_conflict); 165 } 166 167 //------------------------------------------------------------------------------ -
ctrl/firmware/Main/SES/Core/Src/main_task.cpp
r78 r79 10 10 #include "utils.h" 11 11 12 #include "wizchip_conf.h"13 #include "dhcp.h"14 15 static constexpr unsigned ETH_MAX_BUF_SIZE = 2048U;16 static constexpr unsigned SOCKET_DHCP = 1;17 12 18 13 static const char* const TAG = "MAIN"; 19 14 20 15 static constexpr uint16_t delay_ms = 5000; 16 21 17 static constexpr unsigned MAX_CHARS_IN_VOLUME_NAME = 12U; 22 18 static uint8_t volumeName[MAX_CHARS_IN_VOLUME_NAME]; … … 25 21 26 22 static FATFS fs;// __attribute__((section(".DTCM_RAM"))); // Filesystem object 27 static uint8_t dhcp_buffer[ETH_MAX_BUF_SIZE];28 29 wiz_NetInfo gWIZNETINFO = {30 .mac = {0x00, 0x08, 0xdc, 0x6f, 0x00, 0x8a},31 .ip = {192, 168, 11, 109},32 .sn = {255, 255, 255, 0},33 .gw = {192, 168, 11, 1},34 .dns = {8, 8, 8, 8},35 .dhcp = NETINFO_DHCP36 };37 38 23 39 24 FRESULT scan_files (TCHAR* path); 40 25 FRESULT list_dir (const char* path); 41 42 static void ip_assigned(void);43 static void ip_updated(void);44 static void ip_conflict(void);45 static void wizchip_initialize(void);46 static void wizchip_reset(void);47 static void wizchip_check(void);48 static void wizchip_dhcp_init(void);49 26 50 27 //------------------------------------------------------------------------------ … … 53 30 { 54 31 (void)argument; 55 56 wizchip_initialize();57 58 if (gWIZNETINFO.dhcp == NETINFO_DHCP) // DHCP59 {60 wizchip_dhcp_init();61 62 while (DHCP_run() != DHCP_IP_LEASED)63 wiz_delay_ms(1000);64 }65 else // static66 {67 ctlnetwork(CN_SET_NETINFO, &gWIZNETINFO);68 printf("\r\n----------STATIC Net Information--------------\r\n");69 //print_network_information();70 }71 32 72 33 //DHCP_init(0, dhcp_buffer); … … 95 56 } 96 57 97 //------------------------------------------------------------------------------98 99 void wizchip_reset(void)100 {101 HAL_GPIO_WritePin(ETH_SPI_PWR_GPIO_Port, ETH_SPI_PWR_Pin, GPIO_PIN_RESET);102 vTaskDelay(pdMS_TO_TICKS(100U));103 HAL_GPIO_WritePin(ETH_SPI_RST_GPIO_Port, ETH_SPI_RST_Pin, GPIO_PIN_SET);104 vTaskDelay(pdMS_TO_TICKS(65U)); // Min 60.3ms105 }106 107 //------------------------------------------------------------------------------108 109 void wizchip_initialize(void)110 {111 uint8_t W5100S_AdrSet[2][4]= {{2,2,2,2},{2,2,2,2}};112 uint8_t tmp1, tmp2;113 intr_kind temp= IK_DEST_UNREACH;114 115 wizchip_reset();116 117 if (ctlwizchip(CW_INIT_WIZCHIP, (void*)W5100S_AdrSet) == -1)118 printf(">>>>W5100s memory initialization failed\r\n");119 120 if(ctlwizchip(CW_SET_INTRMASK,&temp) == -1)121 printf("W5100S interrupt\r\n");122 123 wizchip_check();124 125 while(1)126 {127 ctlwizchip(CW_GET_PHYLINK, &tmp1 );128 ctlwizchip(CW_GET_PHYLINK, &tmp2 );129 if (tmp1 == PHY_LINK_ON && tmp2 == PHY_LINK_ON) break;130 }131 }132 133 //------------------------------------------------------------------------------134 135 static void ip_assigned(void)136 {137 printf("IP-address was assigned.\n");138 139 uint8_t ip[4];140 getIPfromDHCP(ip);141 printf("IP-address: %u.%u.%u.%u\n", ip[0], ip[1], ip[2], ip[3]);142 143 uint8_t nm[4];144 getSNfromDHCP(nm);145 printf("Subnet mask: %u.%u.%u.%u\n", nm[0], nm[1], nm[2], nm[3]);146 147 uint8_t gw[4];148 getGWfromDHCP(gw);149 printf("Gateway address: %u.%u.%u.%u\n", gw[0], gw[1], gw[2], gw[3]);150 151 uint8_t dns[4];152 getDNSfromDHCP(dns);153 printf("DNS address: %u.%u.%u.%u\n", dns[0], dns[1], dns[2], dns[3]);154 155 printf("Lease time: %u\n", getDHCPLeasetime());156 }157 158 //------------------------------------------------------------------------------159 160 static void ip_updated(void)161 {162 printf("IP-address was updated.\n");163 }164 165 //------------------------------------------------------------------------------166 167 static void ip_conflict(void)168 {169 printf("IP-address conflict!.\n");170 }171 172 //------------------------------------------------------------------------------173 174 void wizchip_check(void)175 {176 // Read version register177 if (getVER() != 0x51) // W5100S178 {179 printf(" ACCESS ERR : VERSIONR != 0x51, read value = 0x%02x\n", getVER());180 while (1);181 }182 }183 184 //------------------------------------------------------------------------------185 186 void wizchip_dhcp_init(void)187 {188 DHCP_init(SOCKET_DHCP, dhcp_buffer);189 reg_dhcp_cbfunc(ip_assigned, ip_updated, ip_conflict);190 }191 192 //------------------------------------------------------------------------------193 58 194 59 /* List contents of a directory */ -
ctrl/firmware/Main/SES/charger.emProject
r78 r79 35 35 c_enforce_ansi_checking="Yes" 36 36 c_preprocessor_definitions="STM32H723xx;_DHCP_DEBUG_" 37 c_user_include_directories="./../CubeMX/Core/Inc;./../CubeMX/Drivers/STM32H7xx_HAL_Driver/Inc;./../CubeMX/Drivers/CMSIS/Device/ST/STM32H7xx/Include;./../CubeMX/Drivers/CMSIS/Core/Include;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/include;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F;./../CubeMX/FATFS/App;./../CubeMX/Middlewares/Third_Party/FatFs/src;./../CubeMX/FATFS/Target;$(ProjectDir)/Core/Inc;$(ProjectDir)/Wiznet/Ethernet/W5100S;$(ProjectDir)/Wiznet/Ethernet;$(ProjectDir)/Wiznet/Internet/DHCP "37 c_user_include_directories="./../CubeMX/Core/Inc;./../CubeMX/Drivers/STM32H7xx_HAL_Driver/Inc;./../CubeMX/Drivers/CMSIS/Device/ST/STM32H7xx/Include;./../CubeMX/Drivers/CMSIS/Core/Include;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/include;./../CubeMX/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F;./../CubeMX/FATFS/App;./../CubeMX/Middlewares/Third_Party/FatFs/src;./../CubeMX/FATFS/Target;$(ProjectDir)/Core/Inc;$(ProjectDir)/Wiznet/Ethernet/W5100S;$(ProjectDir)/Wiznet/Ethernet;$(ProjectDir)/Wiznet/Internet/DHCP;$(ProjectDir)/Wiznet/Application/loopback" 38 38 compiler_color_diagnostics="Yes" 39 39 debug_initial_breakpoint_set_option="Never" … … 69 69 <folder Name="Inc"> 70 70 <file file_name="../CubeMX/Core/Inc/dma.h" /> 71 <file file_name="Core/Inc/eth_thread.h">72 <configuration Name="Debug" build_exclude_from_build="Yes" />73 <configuration Name="Release" build_exclude_from_build="Yes" />74 </file>75 71 <file file_name="Core/Inc/fan_thread.h"> 76 72 <configuration Name="Release" build_exclude_from_build="No" /> … … 79 75 <file file_name="Core/Inc/gsm_rx_thread.h" /> 80 76 <file file_name="Core/Inc/gsm_thread.h" /> 81 <file file_name="Core/Inc/keys_task.h" />82 77 <file file_name="../CubeMX/Core/Inc/main.h" /> 83 <file file_name="Core/Inc/main_task.h" />84 78 <file file_name="../CubeMX/Core/Inc/memorymap.h" /> 85 79 <file file_name="../CubeMX/Core/Inc/rtc.h" /> … … 94 88 <folder Name="Src"> 95 89 <file file_name="../CubeMX/Core/Src/dma.c" /> 96 <file file_name="Core/Src/eth_thread.cpp">97 <configuration Name="Debug" build_exclude_from_build="Yes" />98 <configuration Name="Release" build_exclude_from_build="Yes" />99 </file>100 90 <file file_name="Core/Src/fan_thread.cpp"> 101 91 <configuration Name="Debug" build_exclude_from_build="Yes" /> … … 112 102 <configuration Name="Release" build_exclude_from_build="Yes" /> 113 103 </file> 114 <file file_name="Core/Src/keys_task.cpp" />115 104 <file file_name="../CubeMX/Core/Src/main.c" /> 116 <file file_name="Core/Src/main_task.cpp" />117 105 <file file_name="../CubeMX/Core/Src/memorymap.c" /> 118 106 <file file_name="../CubeMX/Core/Src/rtc.c" /> … … 208 196 </folder> 209 197 </folder> 198 <folder Name="Loopback"> 199 <folder Name="Inc"> 200 <file file_name="Wiznet/Application/loopback/loopback.h" /> 201 </folder> 202 <folder Name="Src"> 203 <file file_name="Wiznet/Application/loopback/loopback.c" /> 204 </folder> 205 </folder> 210 206 </folder> 211 207 </folder> … … 294 290 <file file_name="STM32H7xx/Source/stm32h723xx_Vectors.s" /> 295 291 </folder> 292 <folder Name="Tasks"> 293 <folder Name="Inc"> 294 <file file_name="Core/Inc/eth_task.h" /> 295 <file file_name="Core/Inc/keys_task.h" /> 296 <file file_name="Core/Inc/main_task.h" /> 297 </folder> 298 <folder Name="Src"> 299 <file file_name="Core/Src/eth_task.cpp" /> 300 <file file_name="Core/Src/keys_task.cpp" /> 301 <file file_name="Core/Src/main_task.cpp" /> 302 </folder> 303 </folder> 296 304 </project> 297 305 </solution>
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